Prosecution Insights
Last updated: July 17, 2026
Application No. 18/783,752

SUBSTRATE STRUCTURE

Non-Final OA §102
Filed
Jul 25, 2024
Priority
May 22, 2024 — TW 113118931
Examiner
SAWYER, STEVEN T
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Unimicron Technology Corp.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
748 granted / 1035 resolved
+4.3% vs TC avg
Strong +31% interview lift
Without
With
+30.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
39 currently pending
Career history
1071
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
95.0%
+55.0% vs TC avg
§102
3.2%
-36.8% vs TC avg
§112
1.1%
-38.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1035 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Species 1 (figs. 1-11) directed to claims 1-4, 12-16 and 19-20 in the reply filed on 6/3/2026 is acknowledged. The traversal is on the ground(s) that “it should be no burden on the Examiner to consider all claims in the single application on the ground that the subject matter of all species is sufficiently related such that a search from the subject matter of one species would encompass a search for the subject matter of the other species, and moreover, that prior art applicable to one group would likely be applicable to the other species”. This is not found persuasive because each Specie will have distinct features (as discussed in the restriction requirement) that will require different text and field searches. The requirement is still deemed proper and is therefore made FINAL. Claims 5-11 and 17-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected subject matter. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-4, 12-16 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US PG. Pub. 2025/0046694). Regarding claim 1 – Chen teaches a substrate structure (fig. 5-6, 20/30), comprising: a substrate (SB [paragraph 0055] Chen states, “glass substrate SB”) having a first surface (SB1) and a second surface (SB2) opposite to each other; and a via (TV2 [paragraph 0057] Chen states, “through via TV2”) disposed in the substrate (SB) and penetrating the substrate (SB) along a first direction (vertical direction), wherein the via (TV2) comprises: a first conductive component (MS1) adjacent to the first surface (SB1) of the substrate (SB), wherein the first conductive component (MS1 [paragraph 0082] Chen states, “metal layer M1”) comprises a first seed layer (SEED1 [paragraph 0082] Chen states, “seed layer SEED1”) and a first conductive part (M1); and a second conductive component (MS2) adjacent to the second surface (SB2) of the substrate (SB) and electrically connected to the first conductive component (MS1), wherein the second conductive component (MS2) and the first seed layer (SEED1) form a first contact interface (IN [paragraph 0097] Chen states, “interface IN”), the first contact interface (IN) extends along a second direction (horizontal direction), and the second direction (horizontal direction) is different from the first direction (vertical direction). Regarding claim 2 – Chen teaches the substrate structure as claimed in claim 1, wherein the first conductive component (fig. 6, MS1) has a first sidewall (see sidewall having SEED1 thereon), the second conductive component (MS2) has a second sidewall (see sidewall having SEED2 thereon), and the first sidewall and the second sidewall form a continuous sidewall (figure 6 shows the sidewalls extending in an uninterrupted extension in space [continuous definition, merriam-webster.com]). Regarding claim 3 – Chen teaches the substrate structure as claimed in claim 1, wherein the second conductive component (fig. 6, MS2) comprises a second seed layer (SEED2) and a second conductive part (M2 [paragraph 0090] Chen states, “metal layer M2”), and the second seed layer (SEED2) is in direct contact with the first seed layer (SEED1) to form the first contact interface (IN). Regarding claim 4 – Chen teaches the substrate structure as claimed in claim 3, wherein the first conductive part (fig. 6, M1) and the second conductive part (M2) are separated from each other by the first seed layer (SEED1) and the second seed layer (SEED2). Regarding claim 12 – Chen teaches the substrate structure as claimed in claim 1, wherein an angle between the first direction (fig. 6, vertical direction) and the second direction (horizontal direction) is greater than 0 degrees and less than 180 degrees (figure 6 shows a 90 degree angle between the via and the first contact interface). Regarding claim 13 – Chen teaches the substrate structure as claimed in claim 12, wherein the first direction (fig. 6, vertical direction) and the second direction (horizontal direction) are perpendicular to each other (claimed structure shown in figure 6). Regarding claim 14 – Chen teaches the substrate structure as claimed in claim 1, wherein the first conductive component (fig. 6, MS1) has a first height, the second conductive component (MS2) has a second height, and a ratio of the first height to the second height is between 1:2 and 2:1 (figure 6 shows the heights of each component being the same thereby being 1:1). Regarding claim 15 – Chen teaches the substrate structure as claimed in claim 14, wherein the first height is the same as the second height (fig. 6, claimed structure shown in figure 6). Regarding claim 16 – Chen teaches the substrate structure as claimed in claim 1, wherein the first conductive component (fig. 6, MS1) has a first width, the second conductive component (MS2) has a second width, and the first width is the same as the second width (figure 6 shows a mirror image between the first and second conductive components and therefore have the same widths as claimed). Regarding claim 19 – Chen teaches the substrate structure as claimed in claim 1, wherein the via (figs. 5-6, TV2) further comprises a first conductive protrusion (see top portion of M1 as shown in annotated figure 6 below) and a second conductive protrusion (see top portion of M2 as shown in annotated figure 6 below), wherein the first conductive protrusion is disposed on the first conductive component (MS1) and protrudes from the first surface (SB1) of the substrate (SB), and the second conductive protrusion is disposed on the second conductive component (MS2) and protrudes from the second surface (SB2) of the substrate (SB, claimed structure shown in figure 6). PNG media_image1.png 561 597 media_image1.png Greyscale Regarding claim 20 – Chen teaches the substrate structure as claimed in claim 19, wherein the first conductive component (fig. 6, MS1) has a first width, the second conductive component (MS2) has a second width, the first conductive protrusion (see top portion of M1 as shown in annotated figure 6 above) has a third width, and the second conductive protrusion (see top portion of M2 as shown in annotated figure 6 above) has a fourth width, wherein the third width is greater than the first width, and the fourth width is greater than the second width (claimed structure shown in annotated figure 6 above). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jeong et al. (US PG. Pub. 2025/0081343) discloses a printed circuit board. Vandermeer et al. (US PG. Pub. 2016/0219704) discloses a hermetically sealed through vias. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at 5712722342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN T SAWYER/ Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jul 25, 2024
Application Filed
Jun 25, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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ELECTRONIC COMPONENT EMBEDDED SUBSTRATE AND MANUFACTURING METHOD THEREFOR
2y 10m to grant Granted Jul 14, 2026
Patent 12677375
STEPPED PACKAGE AND RECESSED CIRCUIT BOARD
4y 6m to grant Granted Jul 07, 2026
Patent 12641880
DISPLAY PANEL AND DISPLAY DEVICE
2y 8m to grant Granted May 26, 2026
Patent 12635067
CIRCUIT BOARD
3y 1m to grant Granted May 19, 2026
Patent 12635073
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3y 2m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+30.7%)
2y 5m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1035 resolved cases by this examiner. Grant probability derived from career allowance rate.

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