DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The response filed 08/27/2024 is accepted, in which, claims 8-10 are amended and claims 11-20 are newly added. Claims 1-20 await an action on the merits as follows.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected for indefiniteness.
Regarding claim 10, there is insufficient antecedent basis for the limitations “silicon” and “silicon atomic percentage.” Please see Examiner's amendment below for Examiner's suggested correction.
EXAMINER’S AMENDMENT
An examiner’s amendment to the record appears below. Should the changes and/or additions be unacceptable to applicant, an amendment may be filed as provided by 37 CFR 1.312. To ensure consideration of such an amendment, it MUST be submitted no later than the payment of the issue fee.
Claim 10 would be allowable if written in independent form including all of the limitations of the base claim and any intervening claims and if the above 112b issue were corrected. To correct the 122b issue, Examiner suggests the amendment below.
The application has been amended as follows:
Claim 10. (Currently Amended): The integrated circuit structure of claim 8, wherein the first silicon layer comprises a silicon concentration having a silicon atomic percentage, wherein the silicon concentration has a peak, and the silicon atomic percentage reduces continuously toward the filling metal region.
Allowable Subject Matter
Claims 5, 9, 10, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 5 and 9, the application limits "the first titanium nitride layer and the first silicon layer in combination act as a work- function layer having an n-type work-function." No prior art found in the search discloses this combination. Prior art that utilizes silicon in the gate stack usually calls for polysilicon and makes no mention of TiN. Conversely, prior art that utilizes TiN often uses it to form p-type layers and makes no mention of silicon layers.
Regarding claim 10, no prior art discloses "the silicon atomic percentage reduces continuously toward the filling metal region." Tsai teaches an elemental silicon layer with a TiN layer above it, with the metal fill on the TiN layer. The silicon is only in the silicon layer. No prior art discloses a continuous reduction in silicon up the stack. Tsai (US 20210366775 A1) includes several layers of TiN in the gate stack including a TiN/SI/TiN combination above the work function layer that are deposited in situ to prevent oxidation of both the silicon layer and the work function layer beneath it which provides analogous structure to the instant application but Tsai fails to disclose a continuous decrease in atomic percentage of silicon in the gate stack.
Regarding claim 18, in view of the discussion above for claims 5 and 9, since no prior art discloses a first TiN layer and a first Si layer, no prior art discloses, "a second p-type work function layer over and contacting the first silicon layer; and a second silicon layer over and contacting the second p-type work function layer."
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-8, 11-13, and 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tsai (US 20210366775 A1).
Regarding claim 1, Tsai teaches an integrated circuit structure (198, Fig 19A) comprising:
a semiconductor region (124');
an n-type source/drain region (154) on (shown on) a side (124L: left side of 124') of the semiconductor region (124'); and
a gate stack (G: layers 161/146/168/172/176/178/180/182/183/188/194) over (shown over) the semiconductor region (124'),
the gate stack (G) comprising:
a gate dielectric (161);
a metal-containing layer (168) over (shown over) the gate dielectric (161), wherein
the metal-containing layer (168) comprises:
a bottom portion (168B: bottom horizontal portion) over (shown over) the gate dielectric (161);
a first sidewall portion (168L: left vertical sidewall) and a second sidewall portion (168R: right vertical sidewall) over (shown over) and connecting (shown connecting) to opposite ends of the bottom portion (168B); and
a silicon layer (180) over (shown over) and physically contacting (shown contacting) the metal-containing layer (168).
Regarding claim 2, Tsai teaches the structure of claim 1 and goes on to teach further comprising a filling metal (183, Fig 19A) over (shown over) and contacting (shown contacting) the silicon layer (180).
Regarding claim 3, Tsai teaches the structure of claim 1 and goes on to teach wherein the silicon layer (180, Fig 19A) comprises elemental silicon (elemental silicon, [0041]).
Regarding claim 4, Tsai teaches the structure of claim 1 and goes on to teach wherein the metal-containing layer (168, Fig 19A) by itself has a p-type work function (p-type; it is well known in the art that TiN can act as a p-type work function material).
Regarding claim 6, Tsai teaches the structure of claim 1 and goes on to teach wherein silicon in the gate stack (G, Fig 19A) has a peak silicon atomic percentage (100%, [0041]) in the silicon layer (180), and
wherein silicon atomic percentage (0%) in the metal-containing layer (168; comprised of 100%TiN, [0031]) is lower (lower) than the peak silicon atomic percentage (100%).
Regarding claim 7, Tsai teaches the structure of claim 1 and goes on to teach wherein the metal-containing layer (168, Fig 19A) comprises titanium nitride (TiN, [0031]), and the silicon layer (180) is free from oxygen (not oxidized, [0049]).
Regarding claim 8, Tsai teaches an integrated circuit structure (198, Fig 19A) comprising:
a semiconductor region (124');
a first gate spacer (146L: gate spacer on left of gate stack) and a second gate spacer (146R: gate spacer on right of gate stack) over (shown over) the semiconductor region (124'); and
a gate stack (G: layers 161/168/172/176/178/180/182/183/188/194) over (shown over) the semiconductor region (124') and between (shown between) the first gate spacer (146L) and the second gate spacer (146R),
the gate stack (G) comprising:
a high-k dielectric layer (166);
a first titanium nitride layer (168) over (shown over) and contacting (shown contacting) the high-k dielectric layer (166);
a first silicon layer (180) over (shown over) and contacting (shown contacting) the first titanium nitride layer (168); and
a filling metal region (182/183) over (shown over) the first silicon layer (180).
Regarding claim 11, Tsai teaches the structure of claim 8 and goes on to teach wherein the gate stack (G, Fig 19A) is free from aluminum (shown free from aluminum) in the first titanium nitride layer (168; comprised of only TiN, [0031]) and the first silicon layer (180; comprised of elemental silicon, [0041]).
Regarding claim 12, Tsai teaches the structure of claim 8 and goes on to teach wherein the filling metal region (182/183, Fig 19A) comprises an additional titanium nitride layer (182).
Regarding claim 13, Tsai teaches the structure of claim 8 and goes on to teach wherein the first silicon layer (180, Fig 19A) is free from oxygen (not oxidized, [0049]) therein.
Regarding claim 16, Tsai teaches the structure of claim 8 and goes on to teach wherein the high-k dielectric layer (166, Fig 19A) comprises hafnium oxide (hafnium oxide, [0030]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20210366775 A1) as applied to claims 1-4, 6-8, 11-13, and 16 above, and further in view of the obviousness of duplication of parts.
Regarding claim 14, Tsai teaches the structure of claim 8 and goes on to teach a second titanium nitride layer (182, Fig 19A) over (shown over) and contacting (shown contacting) the first silicon layer (180).
Paragraph [0062] of the instant application states "By depositing silicon on an aluminum-free metal-containing layer in a gate stack of an n-type transistor, the work-function of the gate stack may be reduced to the desirable range for n-type transistors. Accordingly, aluminum-free work-function layers may be formed, and the reliability is improved. By in-situ depositing the metal-containing layer, the silicon-containing layer, and the glue layer, silicon-containing layer is not adversely oxidized."
Tsai teaches forming the TiN capping layer 178 then forming the silicon layer 180 and the TiN glue layer on top sequentially while not breaking vacuum. Similar to the instant application's approach outlined above, Tsai states in paragraph [0049], "If vacuum break occurs, and silicon capping layer 80 (shown as 180 in F19A) is oxidized, the gate resistance will increase, causing the performance of the resulting transistor to degrade." Tsai's method is analogous to the instant application because before any vacuum break occurs, silicon capping layer 180 is not oxidized, (Tsai, [0049]).
Tsai fails to explicitly teach a second silicon layer over and contacting the second titanium nitride layer.
However, section 2144.04 of the MPEP, Subsection VI, states the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. Since the process and motivation of Tsai and the instant application are analogous, forming a second silicon layer on the second TiN layer would have been obvious to one of ordinary skill in the art before the time of filing to more efficiently protect the work-function layer, (Tsai, [0049]).
Regarding claim 15, Tsai teaches the structure of claim 14 but fails to explicitly teach a third titanium nitride layer over and contacting the second silicon layer; and a third silicon layer over and contacting the third titanium nitride layer.
Paragraph [0062] of the instant application states "By depositing silicon on an aluminum-free metal-containing layer in a gate stack of an n-type transistor, the work-function of the gate stack may be reduced to the desirable range for n-type transistors. Accordingly, aluminum-free work-function layers may be formed, and the reliability is improved. By in-situ depositing the metal-containing layer, the silicon-containing layer, and the glue layer, silicon-containing layer is not adversely oxidized."
Tsai teaches forming the TiN capping layer 178 then forming the silicon layer 180 and the TiN glue layer on top sequentially while not breaking vacuum. Similar to the instant application's approach outlined above, Tsai states in paragraph [0049], "If vacuum break occurs, and silicon capping layer 80 (shown as 180 in F19A) is oxidized, the gate resistance will increase, causing the performance of the resulting transistor to degrade." Tsai's method is analogous to the instant application because before any vacuum break occurs, silicon capping layer 180 is not oxidized, (Tsai, [0049]).
Section 2144.04 of the MPEP, Subsection VI, states the court held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. Similar to the discussion above in claim 14, since the process and motivation of Tsai and the instant application are analogous, forming a third titanium nitride layer on the second silicon layer, and then forming a third silicon layer on the third TiN layer would have been obvious to one of ordinary skill in the art before the time of filing to more efficiently protect the work-function layer, (Tsai, [0049]).
Claims 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20210366775 A1), and further in view of Ferng (US 20210126134 A1).
Regarding claim 17, Tsai teaches an integrated circuit structure (198, Fig 19A) comprising:
a semiconductor strip (124');
a gate stack (G: layers 161/146/168/172/176/178/180/182/183/188/194) …,
the gate stack (G) comprising:
a high-k dielectric layer (166);
a first p-type work function layer (176; p-type, [0026]) over (shown over) the high-k dielectric layer (166);
a first silicon layer (180) over (shown over) and contacting (shown contacting) the first p-type work function layer (176); and
a metal-containing glue layer (182) over (shown over) the first silicon layer (180); and
an n-type source/drain region (154; n-type, [0023]) aside (shown aside) of the gate stack (G).
Tsai fails to explicitly teach a semiconductor nanostructure overlapping the semiconductor strip and a gate stack encircling the semiconductor nanostructure.
However, Ferng teaches a semiconductor nanostructure (801, Fig 12A) overlapping (shown overlapping semiconductor strip 303) the semiconductor strip;
a gate stack encircling (gate 903 shown encircling, Fig 9B) the semiconductor nanostructure (801).
Tsai and Ferng are considered analogous to the claimed invention because both are from the same field of endeavor of integrated circuit structures. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Tsai with the features of Ferng to create a structure with a semiconductor nanostructure overlapping the semiconductor strip and a gate stack encircling the semiconductor nanostructure to improve the integration density of various electronic components by reductions in minimum feature size, which allow more components to be integrated into a given area (Ferng, [0003]).
Regarding claim 19, the combination of Tsai and Ferng discloses the structure of claim 17. Tsai goes on to teach wherein the first p-type work function layer (176, Fig 19A) comprises titanium nitride (TiAlN, [0039]).
Regarding claim 20, the combination of Tsai and Ferng discloses the structure of claim 17. Tsai goes on to teach wherein the first silicon layer (180, Fig 19A) comprises elemental silicon (elemental silicon, [0041]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ando (US 20140187028 A1) - TiN sacrificial layers
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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