DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 25 July 2024, 30 October 2024, 21 November 2024, 10 December 2024 and 22 September 2026. The information therein was considered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “gate spacers on opposing sides of a combined region comprising the gate stack, the gate contact plug, and the liner” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “wherein the liner overlaps the gate spacers.” According to parent claim 1, the gate spacers are on opposing sides of a combined region comprising the gate stack, the gate contact plug, and the liner. It is unclear how the gate spacer can be formed on sides of the liner and also be overlapped by the liner. Clarification is required.
Claim 6 recites “wherein the gate contact plug overlaps some portions of the gate spacers.” According to parent claim 1, the gate spacers are on opposing sides of a combined region comprising the gate stack, the gate contact plug, and the liner. It is unclear how the gate spacer can be formed on opposing sides of the gate contact plug and also be overlapped by the gate contact plug. Clarification is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 and 5-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Horak et al. (US 9,064,801) (hereinafter, “Horak”).
Re: independent claim 1, Horak discloses in fig. 7 an integrated circuit structure comprising: a semiconductor region (102); a gate stack (108) over the semiconductor region; a gate contact plug (128) over and electrically connecting to the gate stack; a liner (124) comprising opposing portions on opposite sides of the gate contact plug; gate spacers (112) on opposing sides of a combined region comprising the gate stack (108), the gate contact plug (128), and the liner (124); a source/drain region (106) on a side of the gate stack; and a first inter-layer dielectric (120), wherein the gate spacers (112) and the combined region (108, 128, 124) are in the first inter-layer dielectric (120).
Re: claim 2, Horak discloses in fig. 7 the integrated circuit structure of claim 1, wherein the liner (124) comprises a dielectric material (col 6 ll. 2-7).
Re: claim 3, Horak discloses in fig. 7 the integrated circuit structure of claim 1, wherein the gate contact plug (128) contacts vertical portions of the liner (124) to form vertical interfaces.
Re: claim 5, Horak discloses in fig. 7 the integrated circuit structure of claim 1, wherein the liner (124) overlaps the gate spacers (112) (See 35 U.S.C. 112(b) rejection above.).
Re: claim 6, Horak discloses in fig. 11 the integrated circuit structure of claim 1, wherein the gate contact plug (128) overlaps some portions of the gate spacers (112) (See 35 U.S.C. 112(b) rejection above.).
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. (US 2020/0118873) (hereinafter, “Tsai”).
Re: independent claim 1, Tsai discloses in fig. 18 an integrated circuit structure comprising: a semiconductor region (20); a gate stack (including 62) over the semiconductor region; a gate contact plug (84 or 86) over and electrically connecting to the gate stack; a liner (82 or 50) comprising opposing portions on opposite sides of the gate contact plug; gate spacers (50 or 38) on opposing sides of a combined region comprising the gate stack (including 62), the gate contact plug (84 or 86), and the liner (82 or 50); a source/drain region (42) on a side of the gate stack; and a first inter-layer dielectric (46), wherein the gate spacers (50 or 38) and the combined region (including 62, 84 or 86, 82 or 50) are in the first inter-layer dielectric (46).
Re: claim 2, Tsai discloses in fig. 18 the integrated circuit structure of claim 1, wherein the liner (50) comprises a dielectric material [0025].
Re: claim 3, Tsai discloses in fig. 18 the integrated circuit structure of claim 1, wherein the gate contact plug (84 or 86) contacts vertical portions of the liner (82 or 50) to form vertical interfaces.
Re: claim 4, Tsai discloses in fig. 18 the integrated circuit structure of claim 3 further comprising an etch stop layer (88) over and contacting the first inter-layer dielectric (46) and the gate contact plug (84 or 86), wherein the vertical interfaces extend to contact a bottom surface of the etch stop layer (88).
Re: claim 5, Tsai discloses in fig. 18 the integrated circuit structure of claim 1, wherein the liner (82 or 50) overlaps the gate spacers (50 or 38) (See 35 U.S.C. 112(b) rejection above.).
Re: claim 6, Tsai discloses in fig. 18 the integrated circuit structure of claim 1, wherein the gate contact plug (84 or 86) overlaps some portions of the gate spacers (50 or 38) (See 35 U.S.C. 112(b) rejection above.).
Claim(s) 14-15 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2019/0334008) (hereinafter, “Chen”).
Re: independent claim 14, Chen discloses in figs. 35B and 36 an integrated circuit structure comprising: a semiconductor region (20); a gate stack (58) over the semiconductor region; a gate spacer (56) comprising portions contacting opposing sidewalls of the gate stack; a dielectric liner (64) over the gate stack, wherein a first outer edge of the dielectric liner (64) is vertically aligned to a second outer edge of the gate spacer (56); a contact etch stop layer (37A) contacting both of the first outer edge of the dielectric liner (64) and the second outer edge of the gate spacer (56); and a gate contact plug (66B) in a region encircled by the dielectric liner (64) (fig. 36), wherein the gate contact plug (66B) contacts a top surface of the gate stack (58).
Re: claim 15, Chen discloses in figs. 35B and 36 the integrated circuit structure of claim 14, wherein the gate contact plug (66B) physically contacts the dielectric liner (64).
Re: claim 19, Chen discloses in figs. 35B and 36 the integrated circuit structure of claim 14, wherein a first top surface of the gate spacer (56) is substantially coplanar with a second top surface of the gate stack (58).
Re: claim 20, Chen discloses in figs. 35B and 36 the integrated circuit structure of claim 14, wherein the gate contact plug comprises: a barrier layer; and a metallic region over the barrier layer [0056].
Allowable Subject Matter
Claims 7-13 are allowed.
Claims 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 7, an integrated circuit structure comprising: a semiconductor fin; a gate stack on a first top surface and sidewalls of the semiconductor fin; a gate contact plug over and electrically connected to the gate stack; a dielectric liner encircling the gate contact plug, wherein bottom surfaces of both of the gate contact plug and the dielectric liner are in contact with a second top surface of the gate stack; an etch stop layer over and contacting the dielectric liner; and a gate spacer comprising a first portion overlapped by a second portion of the dielectric liner, wherein the gate spacer encircles the gate stack; and as recited in claim 16, the integrated circuit structure of claim 14 further comprising a source/drain region aside of the gate spacer, wherein the contact etch stop layer comprises a horizontal portion over and contacting the source/drain region; and as recited in claim 17, integrated circuit structure of claim 14 further comprising: a first inter-layer dielectric overlapping a part of the contact etch stop layer; and a second inter-layer dielectric overlapping the gate stack.
Conclusion
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 9/28/2026
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