DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on May 4, 2026.
Claims 1-20 are pending. Claims 1, 3 ,6, 9, 13 and 16 are amended. Claims 1, 9 and 16 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on May 4, 2026. These drawings are acceptable.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-7, 9 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Brandl et al. (US 20210201986) in view of Ahmad et al. (US 20140032947).
Regarding independent claim 1, Brandl et al. disclose a device [Fig. 1: 100] comprising:
a control circuit [Fig. 8: 810] exit a low power state of a memory [see Fig. 11: step 1130 with respect to Fig. 10: step 1030, on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory. For S3, the self-refresh state machine MOP array (small code for optimized state machine) is programmed to exit self-refresh and to update any DRAM device state for the target power management state (memory P-state) at step 1035, para. 76] by:
restoring the context of the memory controller [Fig.11: at step 1130, step 1030 from method 1000 is followed, including on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory, para. 80].
However, Brandl et al. are silent with respect to performing a partial context restore of a memory controller of the memory; and
completing, using the partial context, a complete context restore of the memory controller.
Ahmad et al. teach in Figure 1 a system power management unit (SPMU) 102 having a micro-controller 104, a micro-coded engine 106, an on-die storage 108 (e.g., an on-die SRAM), and a context save/restore engine 110 [para. 22]. Ahmad et al. further teach when the memory controller 112 has been power-ungated (returning from a low-power state), the context save/restore engine 110 may restore the memory controller context (from the on-die storage 108) which was saved from a previous context prior to power gating, and restores the same clock frequency also [para. 24]. At least one context is stored in the on-die storage 108 and any remaining contexts are stored in the DRAM module 118 [para. 25]. Ahmad et al. also teach that to reduce memory controller save/restore latencies, a context may be grouped into three groups of context data: static context data that is pre-computed by training, pseudo-static context data that is configured at boot time, and dynamic context that is dynamically generated by the memory controller 112 [para. 26].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Ahmad et al. to the teachings of Brandl et al. such that modifying the restore process of Brandl et al. to first restore a partial context from memory device as taught by Ahmad et al. and then use that partial context to restore the remaining context, thereby doing so would reduce exit latency and reduce the amount of fast non-volatile storage needed.
Regarding claim 2, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 1.
Furthermore, Brandl et al. disclose the control circuit is configured to preserve the context of the memory controller by saving at least a portion of the context to a non-volatile memory device [see Fig. 11: at step 1110, prior to restore, the DRAM controller and the DDR PHY settings, are stored in a non-volatile memory location, para. 78].
Regarding claim 5, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 1.
Furthermore, Brandl et al. disclose the low power state corresponds to a self-refresh state of the memory [a “low power state” means a state that saves power compared to another state. For example, DDR4 SDRAM supports two low power states known as self-refresh and precharge power down, para. 71].
Regarding claim 6, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 1.
Furthermore, Brandl et al. disclose the control circuit is further configured to exit the low power state of the memory [see Fig. 11: step 1130 with respect to Fig. 10: step 1030, on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory. For S3, the self-refresh state machine MOP array (small code for optimized state machine) is programmed to exit self-refresh and to update any DRAM device state for the target power management state (memory P-state) at step 1035, para. 76] by:
exit power gating a physical layer of the memory [DDR4 SDRAM supports two low power states known as self-refresh and precharge power down, so when exiting low power modes mean exiting power down the DRAM controller and DDR PHY].
Regarding claim 7, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 6.
Furthermore, Brandl et al. disclose the control circuit is configured to restore the context of the memory controller by restoring the context from a non-volatile memory device [Fig.11: at step 1130, step 1030 from method 1000 is followed, including on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory, para. 80].
Regarding independent claim 9, Brandl et al. disclose a system [Fig. 1: 100] comprising:
a memory [Fig. 5: 500] comprising a memory controller [Fig. 5: 514] and a physical layer [Fig. 5: 516] corresponding to a plurality of logic components [para. 46];
a non-volatile memory device [Fig. 1: 104, the memory 104 includes a volatile or non-volatile memory, for example, random access memory (RAM), dynamic RAM, or a cache, para. 19];
a processor [Fig. 1: 102, para. 19]; and
a control circuit [Fig. 8: 810] configured to:
enter a low power state of a memory [memory controller 810 places memory module 830 into a low power state, para. 61] by:
preserving a context of a memory controller of the memory by saving at least a portion of the context to the non-volatile memory device [see Fig. 11: at step 1110, prior to restore, the DRAM controller and the DDR PHY settings, are stored in a non-volatile memory location, para. 78]; and
power gating a physical layer of the memory [see Fig. 11: step 1115-1120, at step 1115, in DDR4 mode, the DRAMs are then set into self-refresh mode by the DRAM controller. The DRAM controller and DDR PHY are then powered down to save total system power or the entire system may have power removed at step 1120, para. 79]; and
exit a low power state of a memory [see Fig. 11: step 1130 with respect to Fig. 10: step 1030, on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory. For S3, the self-refresh state machine MOP array (small code for optimized state machine) is programmed to exit self-refresh and to update any DRAM device state for the target power management state (memory P-state) at step 1035, para. 76] by:
restoring the context of the memory controller [Fig.11: at step 1130, step 1030 from method 1000 is followed, including on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory, para. 80].
However, Brandl et al. are silent with respect to performing a partial context restore of a memory controller using the portion of the context; and
completing, using the partial context, a complete context restore of the memory controller.
Ahmad et al. teach in Figure 1 a system power management unit (SPMU) 102 having a micro-controller 104, a micro-coded engine 106, an on-die storage 108 (e.g., an on-die SRAM), and a context save/restore engine 110 [para. 22]. Ahmad et al. further teach when the memory controller 112 has been power-ungated (returning from a low-power state), the context save/restore engine 110 may restore the memory controller context (from the on-die storage 108) which was saved from a previous context prior to power gating, and restores the same clock frequency also [para. 24]. At least one context is stored in the on-die storage 108 and any remaining contexts are stored in the DRAM module 118 [para. 25]. Ahmad et al. also teach that to reduce memory controller save/restore latencies, a context may be grouped into three groups of context data: static context data that is pre-computed by training, pseudo-static context data that is configured at boot time, and dynamic context that is dynamically generated by the memory controller 112 [para. 26].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Ahmad et al. to the teachings of Brandl et al. such that modifying the restore process of Brandl et al. to first restore a partial context from memory device as taught by Ahmad et al. and then use that partial context to restore the remaining context, thereby doing so would reduce exit latency and reduce the amount of fast non-volatile storage needed.
Regarding claim 12, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 9.
Furthermore, Brandl et al. disclose the low power state corresponds to a self-refresh state of the memory [a “low power state” means a state that saves power compared to another state. For example, DDR4 SDRAM supports two low power states known as self-refresh and precharge power down, para. 71].
Regarding claim 13, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 9.
Furthermore, Brandl et al. disclose the control circuit is further configured to exit the low power state of the memory [see Fig. 11: step 1130 with respect to Fig. 10: step 1030, on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory. For S3, the self-refresh state machine MOP array (small code for optimized state machine) is programmed to exit self-refresh and to update any DRAM device state for the target power management state (memory P-state) at step 1035, para. 76] by:
exit power gating the physical layer of the memory [DDR4 SDRAM supports two low power states known as self-refresh and precharge power down, so when exiting low power modes mean exiting power down the DRAM controller and DDR PHY].
Regarding claim 14, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 13.
Furthermore, Brandl et al. disclose the control circuit is configured to restore the context of the memory controller by restoring the context from a non-volatile memory device [Fig.11: at step 1130, step 1030 from method 1000 is followed, including on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory, para. 80].
Claims 3, 8, 10, 15-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Brandl et al. (US 20210201986) in view of Ahmad et al. (US 20140032947) as applied to claims 1, 6, 9 and 13 above and further in view of Biswas (US 20180061484).
Regarding claim 3, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 1.
However, Brandl et al. in combination with Ahmad et al. are silent with respect to the control circuit is configured to preserve the context of the memory controller by supplying a retention supply voltage to one or more registers of the memory controller while power gating the physical layer.
Biswas teaches the control circuit is configured to supply a retention supply voltage to one or more registers of the memory controller while power gating the physical layer [in response to self refresh mode entry, the memory controller 14 may be configured to freeze the value of the refresh timer register 16. For example, if the memory controller 14 is to be powered down, the refresh timer register 16 may be placed on retention voltage to ensure the power is maintained, para. 23].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Biswas to the teachings of Brandl et al. in combination with Ahmad et al. such that incorporating Biswas’s retention voltage technique into the memory controller as taught by Brandl et al. in combination with Ahmad et al. while power gating the physical layer to ensure data integrity and avoid data loss [see Biswas’s para 3-4].
Regarding claim 8, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 6.
However, Brandl et al. in combination with Ahmad et al. are silent with respect to exiting the power gating further comprises deactivating a retention supply voltage to one or more registers of the memory controller.
Biswas to exiting the power gating further comprises deactivating a retention supply voltage to one or more registers of the memory controller [when self refresh mode is exited and the refresh timer updates restart, the correct amount of time during normal mode may pass prior to the next refresh even if the interval is interrupted by time in self refresh mode, para. 23. A person having ordinary skill in the art would understand that once the normal operation is resumed, the retention condition is no longer needed and would be deactivated].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Biswas to the teachings of Brandl et al. in combination with Ahmad et al. such that incorporating Biswas’s retention voltage technique into the memory controller as taught by Brandl et al. in combination with Ahmad et al. while power gating the physical layer to ensure data integrity and avoid data loss [see Biswas’s para 3-4].
Regarding claim 10, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 9.
However, Brandl et al. in combination with Ahmad et al. are silent with respect to the control circuit is configured to preserve the context of the memory controller by supplying a retention supply voltage to one or more registers of the memory controller while power gating the physical layer.
Biswas teaches the control circuit is configured to supply a retention supply voltage to one or more registers of the memory controller while power gating the physical layer [in response to self refresh mode entry, the memory controller 14 may be configured to freeze the value of the refresh timer register 16. For example, if the memory controller 14 is to be powered down, the refresh timer register 16 may be placed on retention voltage to ensure the power is maintained, para. 23].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Biswas to the teachings of Brandl et al. in combination with Ahmad et al. such that incorporating Biswas’s retention voltage technique into the memory controller as taught by Brandl et al. in combination with Ahmad et al. while power gating the physical layer to ensure data integrity and avoid data loss [see Biswas’s para 3-4].
Regarding claim 15, Brandl et al. in combination with Ahmad et al. teach the limitations with respect to claim 13.
However, Brandl et al. in combination with Ahmad et al. are silent with respect to exiting the power gating further comprises deactivating a retention supply voltage to one or more registers of the memory controller.
Biswas to exiting the power gating further comprises deactivating a retention supply voltage to one or more registers of the memory controller [when self refresh mode is exited and the refresh timer updates restart, the correct amount of time during normal mode may pass prior to the next refresh even if the interval is interrupted by time in self refresh mode, para. 23. A person having ordinary skill in the art would understand that once the normal operation is resumed, the retention condition is no longer needed and would be deactivated].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Biswas to the teachings of Brandl et al. in combination with Ahmad et al. such that incorporating Biswas’s retention voltage technique into the memory controller as taught by Brandl et al. in combination with Ahmad et al. while power gating the physical layer to ensure data integrity and avoid data loss [see Biswas’s para 3-4].
Regarding independent claim 16, Brandl et al. disclose a method comprising:
initiating, in response to a low power entry condition, entry to a low power state of a memory [memory controller 810 places memory module 830 into a low power state, para. 61];
saving a context of a memory controller of the memory to a non-volatile memory device [see Fig. 11: at step 1110, prior to restore, the DRAM controller and the DDR PHY settings, are stored in a non-volatile memory location, para. 78];
power gating a plurality of logic components of the memory [see Fig. 11: step 1115-1120, at step 1115, in DDR4 mode, the DRAMs are then set into self-refresh mode by the DRAM controller. The DRAM controller and DDR PHY are then powered down to save total system power or the entire system may have power removed at step 1120, para. 79]
initiating, in response to a low power exit condition, exit of the low power state of the memory [see Fig. 11: step 1130 with respect to Fig. 10: step 1030, on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory. For S3, the self-refresh state machine MOP array (small code for optimized state machine) is programmed to exit self-refresh and to update any DRAM device state for the target power management state (memory P-state) at step 1035, para. 76] by restoring the context of the memory controller [Fig.11: at step 1130, step 1030 from method 1000 is followed, including on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory, para. 80].
However, Brandl et al. are silent with respect to retaining a retention supply voltage to power a register of the memory while power gating the plurality of logic components and exit of the low power state of the memory by performing a partial context restore of a memory controller; and
completing, using the partial context, a complete context restore of the memory controller.
Biswas teaches retaining a retention supply voltage to power a register of the memory while power gating the plurality of logic components [in response to self refresh mode entry, the memory controller 14 may be configured to freeze the value of the refresh timer register 16. For example, if the memory controller 14 is to be powered down, the refresh timer register 16 may be placed on retention voltage to ensure the power is maintained, para. 23].
Furthermore, Ahmad et al. teach in Figure 1 a system power management unit (SPMU) 102 having a micro-controller 104, a micro-coded engine 106, an on-die storage 108 (e.g., an on-die SRAM), and a context save/restore engine 110 [para. 22]. Ahmad et al. further teach when the memory controller 112 has been power-ungated (returning from a low-power state), the context save/restore engine 110 may restore the memory controller context (from the on-die storage 108) which was saved from a previous context prior to power gating, and restores the same clock frequency also [para. 24]. At least one context is stored in the on-die storage 108 and any remaining contexts are stored in the DRAM module 118 [para. 25]. Ahmad et al. also teach that to reduce memory controller save/restore latencies, a context may be grouped into three groups of context data: static context data that is pre-computed by training, pseudo-static context data that is configured at boot time, and dynamic context that is dynamically generated by the memory controller 112 [para. 26].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Biswas and Ahmad et al. to the teachings of Brandl et al. such that incorporating Biswas’s retention voltage technique into the memory controller as taught by Brandl et al. while power gating the physical layer to ensure data integrity and avoid data loss [see Biswas’s para 3-4] and modifying the restore process of Brandl et al. to first restore a partial context from memory device as taught by Ahmad et al. and then use that partial context to restore the remaining context, thereby doing so would reduce exit latency and reduce the amount of fast non-volatile storage needed.
Regarding claim 18, Brandl et al. in combination with Biswas and Ahmad et al. teach the limitations with respect to claim 16.
Furthermore, Brandl et al. disclose the low power state corresponds to a self-refresh state of the memory [a “low power state” means a state that saves power compared to another state. For example, DDR4 SDRAM supports two low power states known as self-refresh and precharge power down, para. 71].
Regarding claim 19, Brandl et al. in combination with Biswas and Ahmad et al. teach the limitations with respect to claim 16.
Furthermore, Brandl et al. disclose further comprising exiting the low power state of the memory [see Fig. 11: step 1130 with respect to Fig. 10: step 1030, on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory. For S3, the self-refresh state machine MOP array (small code for optimized state machine) is programmed to exit self-refresh and to update any DRAM device state for the target power management state (memory P-state) at step 1035, para. 76].
Regarding claim 20, Brandl et al. in combination with Biswas and Ahmad et al. teach the limitations with respect to claim 19.
Furthermore, Brandl et al. disclose further exiting the low power state further comprises:
exit power gating the plurality of logic components of the memory [DDR4 SDRAM supports two low power states known as self-refresh and precharge power down, so when exiting low power modes mean exiting power down the DRAM controller and DDR PHY]; and
restoring the context of the memory controller by restoring the context from the non-volatile memory device [Fig.11: at step 1130, step 1030 from method 1000 is followed, including on system resume, the BIOS restores the DRAM controller and the DDR PHY settings from the non-volatile memory, para. 80].
Moreover, Biswas teaches deactivating the retention supply voltage to the register [when self refresh mode is exited and the refresh timer updates restart, the correct amount of time during normal mode may pass prior to the next refresh even if the interval is interrupted by time in self refresh mode, para. 23. A person having ordinary skill in the art would understand that once the normal operation is resumed, the retention condition is no longer needed and would be deactivated].
Claims 4, 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Brandl et al. (US 20210201986) in view of Biswas (US 20180061484) and Ahmad et al. (US 20140032947) as applied to claims 3, 10 and 16 above and further in view of Price et al. (US 20140139197).
Regarding claims 4 and 11, Brandl et al. in combination with Biswas and Ahmad et al. teach the limitations with respect to claims 3 and 10.
However, Brandl et al. in combination with Biswas and Ahmad et al. are silent with respect to the control circuit is configured to supply the retention supply voltage by enabling a bypass mode of a voltage regulator.
Price et al. teach the control circuit is configured to supply the retention supply voltage by enabling a bypass mode of a voltage regulator [a bypass mode circuit may be configured to perform the ON override by shorting the pass gate control line, in response to receiving the bypass mode ON signal, to a power rail having the pass gate ON hard voltage, para. 5-7].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Price et al. to the teachings of Brandl et al. in combination with Biswas and Ahmad et al. such that incorporating Price et al.’s bypass mode voltage regulator feature into the power supply voltage of Brandl et al. in combination with Biswas and Ahmad et al. to provide the retention supply voltage as required by claim 4.
Regarding claim 17, Brandl et al. in combination with Biswas and Ahmad et al. teach the limitations with respect to claim 16.
However, Brandl et al. in combination with Biswas and Ahmad et al. are silent with respect to retaining the retention supply voltage further comprises enabling a bypass mode of a voltage regulator.
Price et al. teach retaining the retention supply voltage further comprises enabling a bypass mode of a voltage regulator [a bypass mode circuit may be configured to perform the ON override by shorting the pass gate control line, in response to receiving the bypass mode ON signal, to a power rail having the pass gate ON hard voltage, para. 5-7].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Price et al. to the teachings of Brandl et al. in combination with Biswas and Ahmad et al. such that incorporating Price et al.’s bypass mode voltage regulator feature into the power supply voltage of Brandl et al. in combination with Biswas and Ahmad et al. to provide the retention supply voltage as required by claim 4.
Response to Arguments
Applicant’s arguments with respect to claims 1, 9 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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