DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to amendment filed on March 23, 2026.
Claims 1-3, 5, 7, 9-12, 14, 16, and 18-20 have been amended.
Claims 8 and 17 are canceled.
The objections and rejections from the prior correspondence that are not restated herein are withdrawn.
Response to Arguments
Applicant's arguments filed on March 23, 2026 have been fully considered but are moot because the arguments allege that only the newly added limitations are not taught by the prior art of record. It should be noted that a new prior art reference to LAMERES in combination with FENDER and YAMAKI teaches the newly added limitations as shown in the rejections below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9-10, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over FENDER (Patent No.: US 9698794 B1), hereafter FENDER, in view of LAMERES (Patent No.: US 11966284 B1), hereafter LAMERES, and YAMAKI (Pub. No.: US 20130021832 A1), hereafter YAMAKI.
Regarding claim 1, FENDER teaches:
A method, comprising: detecting, by computer hardware, logical memory instances defined in a circuit design specified as a register-transfer level description (FENDER C2:L50-61 teach region defragmentation of a programmable integrated circuit device such as an FPGA (i.e. circuit design specified as a register-transfer level description), where defragmenting memory inherently requires accessing logical memory instances based on address (see FENDER C7:L15-20, which teaches memory is not physically migrated but rather remapped to be accessible from the newly assigned subregion through the means of a hardware addressing remapping function. Virtual memory address translation can be segment-based, paged-based, and/or the like); C4:L6-11 teach free space fragmentation may occur, e.g., while subregions 208 a-b are free, they are fragmented, instead of forming an available contiguous region. When a new function D (202 d) is to be loaded onto the FPGA 201, the fragmented FPGA, e.g., at 207, cannot provide an available region large enough for function D.),
generating, by the computer hardware, a group including a plurality of the logical memory instances that are compatible with memory merger criteria; merging the plurality of logical memory instances of the group into a composite logical memory (FENDER C4:L12-24 teach region defragmentation 300 of a running virtualized FPGA system using live region migration within the FPGA. At 301, which is similar to the fragmented FPGA 206 in FIG. 2 after function A has been released, defragmentation can be implemented by migrating function B to a new region such that the original subregion associated with function B can be released to coalesce with other available subregions. To achieve this, a new function B′ can be loaded at 303, which may be configured to perform a similar task as function B. The new function B′ can take up a previously fragmented space.);
replacing, by the computer hardware and within the circuit design, the plurality of logical memory instances of the group with the composite logical memory (FENDER C3:L1-5 teach defragmentation via region migration can be implemented to release and coalesce adjacent subregions such that the coalesced subregions can provide sufficient resources for the new function for the virtualized FPGA; C5:L4-7 teach either with a precompiled region-specific bitstream or a region-remappable bitstream, an FPGA function can be moved to a different location on the FPGA fabric while preserving the same function to be performed).
FENDER does not appear to explicitly teach each logical memory instance having a size defined in the circuit design that partially occupies an amount of memory provided by one or more memory primitives of a target programmable integrated circuit (IC) device that implement the logical memory instance, wherein each memory primitive is a predetermined memory circuit block of the target programmable IC; wherein the composite logical memory requires fewer memory primitives of the target programmable IC device to implement than a number of memory primitives needed to implement the plurality of logical memory instances as individual memories.
However, FENDER in view of LAMERES teaches each logical memory instance having a size defined in the circuit design that partially occupies an amount of memory provided by one or more memory primitives of a target programmable integrated circuit (IC) device that implement the logical memory instance, wherein each memory primitive is a predetermined memory circuit block of the target programmable IC (LAMERES C13:L30-54 teach all start addresses and sizes for components in the memory map may be defined in a VHDL package file and constrained to fit the FPGA selected. The IMEM and DMEM components 203-1 and 203-2 may be required for basic operation, with each set to 4096 bytes (4 kilobytes) of memory in one non-limiting example).
Accordingly, it would have been obvious to a person having ordinary skill in the art at the time of effective filing of the invention, to have combined FENDER and LAMERES and obtained coalescing regions on a programmable logic device having components in the memory defined in a VHDL package file. One of ordinary skill in the art would have been motivated to make such a combination because all of the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods (e.g. having components in the memory defined in a VHDL package file) with no change in their respective functions (e.g. coalescing regions on a programmable logic device), and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the effective filing of the invention (e.g. a programmable logic device having components in the memory defined in a VHDL package file coalescing regions on the device).
FENDER in view of LAMERES does not appear to explicitly teach wherein the composite logical memory requires fewer memory primitives of the target programmable IC device to implement than a number of memory primitives needed to implement the plurality of logical memory instances as individual memories.
However, FENDER in view of LAMERES and YAMAKI teaches wherein the composite logical memory requires fewer memory primitives of the target programmable IC device to implement than a number of memory primitives needed to implement the plurality of logical memory instances as individual memories (YAMAKI [0164] teaches a determination is made as to which SRAM module is to be placed in which memory block, as to which memory block is to be placed in which memory group, as to the memory module coupling path in each memory block, and as to the coupling path among memory blocks, where memory groups are determined by grouping SRAM modules (i.e. memory primitives) at close physical locations such that the total storage capacity of each memory group is equal to or less than a predetermined value (i.e. uses less than one or more memory primitives); [0167-0170] teach the smallest storage capacity of each memory module is employed as the criterion as well as other types of criterion, where memory groups are determined by grouping SRAM modules at close physical locations such that the total storage capacity of each memory group is equal to or less than a predetermined value (i.e. requires fewer memory primitives of the target programmable IC device to implement than a number of memory primitives needed to implement the plurality of logical memory instances as individual memories); [0042-0043] teach selecting memory modules having largest storage capacity in the memory block to ensure that when it is commanded to cancel the lower power consumption state for memory modules in a downstream memory block, substantially all memory modules in an upstream memory block have already exited the lower power consumption state. Thus, it is possible to prevent inrush current peaks from overlapping between memory blocks).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FENDER, LAMERES, and YAMAKI before them, to include YAMAKI’s memory selection in FENDER and LAMERES’s coalescing regions on a programmable logic device. One would have been motivated to make such a combination in order to provide greater storage capacity as taught by YAMAKI ([ABST]).
Regarding claim 10, the claim recites similar limitation as corresponding claim 1 and is rejected for similar reasons as claim 1 using similar teachings and rationale. FENDER also teaches A system, comprising: a hardware processor capable of executing operations (see FENDER Fig. 1).
Regarding claim 19, the claim recites similar limitation as corresponding claim 1 and is rejected for similar reasons as claim 1 using similar teachings and rationale. FENDER also teaches A computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the program instructions are executable by computer hardware to cause the computer hardware to initiate executable operations (see FENDER claim 19).
Regarding claim 9, FENDER in view of LAMERES and YAMAKI teaches the elements of claim 1 as outlined above. YAMAKI also teaches:
placing and routing the circuit design including the composite logical memory (YAMAKI [0164] teaches in the place and route design of the microcomputer 1, a determination is made as to which SRAM module is to be placed in which memory block, as to which memory block is to be placed in which memory group, as to the memory module coupling path in each memory block, and as to the coupling path among memory blocks).
The same motivation that was utilized for combining FENDER, LAMERES, and YAMAKI as set forth in claim 1 is equally applicable to claim 9.
Regarding claim 18, the claim recites similar limitation as corresponding claim 9 and is rejected for similar reasons as claim 9 using similar teachings and rationale.
Claims 2-7, 11-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over FENDER in view of LAMERES and YAMAKI as applied to claims 1, 10, and 19 above, and further in view of SCHOPP (Pub. No.: US 20050066143 A1), hereafter SCHOPP.
Regarding claim 2, FENDER in view of LAMERES and YAMAKI teaches the elements of claim 1 as outlined above. FENDER also teaches:
wherein the generating the group comprises: comparing attributes of the logical memory instances with the memory merger criteria (FENDER C4:L39-51 teach the FPGA system can respond to a request to move function B 311a from its original subregion to a new subregion at 311b by looking up a corresponding configuration bitstream that has been precompiled to implement for a same function as the function B but to be placed at the new subregion, referred to as function B′, and then loading the corresponding configuration bitstream in the FPGA at the subregion location 311b. Because the corresponding configuration bitstream for function B′ can implement the same function as the original function B 311a, function B′ has the ability to accept state from the original function B 311a; see also C5:L34-36 & Fig. 4 #407, where in response to a new function loading request when the FPGA does not have a large enough contiguous region).
FENDER in view of LAMERES and YAMAKI does not appear to explicitly teach removing from the group each logical memory instance that is incompatible with the memory merger criteria.
However, SCHOPP teaches the limitation (see SCHOPP Fig. 4, where free/allocated status for preceding and succeeding blocks are determined (48), and locks are initiated on only heaps with free preceding or succeeding blocks (50), where blocks that do not meet such criteria are not considered for coalescing per rules, which is seen as being removed from the group/incompatible).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FENDER, LAMERES, YAMAKI, and SCHOPP before them, to include SCHOPP’s method of coalescing blocks of memory within multiple memory heaps in FENDER, LAMERES, and YAMAKI’s coalescing regions on a programmable logic device. One would have been motivated to make such a combination in order to provide an efficient method whereby memory could be coalesced across memory heap boundaries as taught by SCHOPP ([0006]).
Regarding claim 3, FENDER in view of LAMERES and YAMAKI teaches the elements of claim 1 as outlined above. FENDER in view of LAMERES and YAMAKI does not appear to explicitly teach:
wherein the memory merger criteria specify validation rules for merging logical memory instances of the circuit design in at least one dimension.
However, SCHOPP teaches the limitation (SCHOPP [0027] teaches coalescing of memory blocks according to designated coalescing rules, for example (1) if both the preceding and succeeding adjacent blocks of memory are present within the same memory heap, the newly freed memory block is coalesced with both of those blocks and moved to the heap containing those two blocks; (2) if both the preceding and succeeding adjacent memory blocks are free but are present in two different heaps, the newly freed memory block is coalesced with the larger of the preceding and succeeding memory block in the heap which previously contained the newly freed memory block; and (3) if only one of the preceding or succeeding adjacent memory blocks is free, it should be coalesced with the newly freed memory block, thus providing a partial coalescing of two memory blocks).
Accordingly, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of FENDER, LAMERES, YAMAKI, and SCHOPP before them, to include SCHOPP’s method of coalescing blocks of memory within multiple memory heaps in FENDER, LAMERES, and YAMAKI’s coalescing regions on a programmable logic device. One would have been motivated to make such a combination in order to provide an efficient method whereby memory could be coalesced across memory heap boundaries as taught by SCHOPP ([0006]).
Regarding claim 4, FENDER in view of LAMERES, YAMAKI, and SCHOPP teaches the elements of claim 3 as outlined above. SCHOPP also teaches:
wherein the at least one dimension is horizontal (see SCHOPP [0027], where (1) if both the preceding and succeeding adjacent blocks of memory are present within the same memory heap, the newly freed memory block is coalesced with both of those blocks and moved to the heap containing those two blocks).
The same motivation that was utilized for combining FENDER, LAMERES, YAMAKI, and SCHOPP as set forth in claim 3 is equally applicable to claim 4.
Regarding claim 5, FENDER in view of LAMERES, YAMAKI, and SCHOPP teaches the elements of claim 4 as outlined above. FENDER in view of LAMERES, YAMAKI, and SCHOPP also teaches:
wherein the validation rules include: each logical memory instance of the group uses same addressing for read operations and for write operations; and each logical memory instance of the group uses same control signals (FENDER Fig. 1 illustrates a single memory bus connecting to On Chip Memory 112 and Memory 115, where C3:L13-24 teach read/write operations for memory; SCHOPP [0021] also teaches using memory addresses to identify memory blocks, where Fig. 2 illustrates a single bus to access memory blocks in each heap).
The same motivation that was utilized for combining FENDER, LAMERES, YAMAKI, and SCHOPP as set forth in claim 3 is equally applicable to claim 5.
Regarding claim 6, FENDER in view of LAMERES, YAMAKI, and SCHOPP teaches the elements of claim 3 as outlined above. SCHOPP also teaches:
wherein the at least one dimension is vertical (see SCHOPP [0027], where (2) if both the preceding and succeeding adjacent memory blocks are free but are present in two different heaps, the newly freed memory block is coalesced with the larger of the preceding and succeeding memory block in the heap which previously contained the newly freed memory block).
The same motivation that was utilized for combining FENDER, YAMAKI, and SCHOPP as set forth in claim 3 is equally applicable to claim 6.
Regarding claim 7, FENDER in view of LAMERES, YAMAKI, and SCHOPP teaches the elements of claim 6 as outlined above. FENDER in view of LAMERES, YAMAKI, and SCHOPP also teaches:
wherein the validation rules include: each logical memory instance of the group has a read address bus and a write address bus with a plurality of common address bits (see FENDER Fig. 1 & C3:L13-24 and SCHOPP Fig. 2 & [0021] as outlined in claim 5 above, where single memory bus is used to access memory blocks in the heap for read/write operations);
the plurality of logical memory instances of the group form a contiguous address space (see SCHOPP [0027], where the newly freed memory blocks are coalesced and moved to the heap containing those two blocks).
The same motivation that was utilized for combining FENDER, LAMERES, YAMAKI, and SCHOPP as set forth in claim 3 is equally applicable to claim 7.
Regarding claim 11, the claim recites similar limitation as corresponding claim 2 and is rejected for similar reasons as claim 2 using similar teachings and rationale.
Regarding claim 12, the claim recites similar limitation as corresponding claim 3 and is rejected for similar reasons as claim 3 using similar teachings and rationale.
Regarding claim 13, the claim recites similar limitation as corresponding claim 4 and is rejected for similar reasons as claim 4 using similar teachings and rationale.
Regarding claim 14, the claim recites similar limitation as corresponding claim 5 and is rejected for similar reasons as claim 5 using similar teachings and rationale.
Regarding claim 15, the claim recites similar limitation as corresponding claim 6 and is rejected for similar reasons as claim 6 using similar teachings and rationale.
Regarding claim 16, the claim recites similar limitation as corresponding claim 7 and is rejected for similar reasons as claim 7 using similar teachings and rationale.
Regarding claim 20, the claim recites similar limitation as corresponding claim 3 and is rejected for similar reasons as claim 3 using similar teachings and rationale.
Conclusion
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/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175
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