DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 4, 7, 9, 16 and 17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lien et al. (US Pat Pub 2025/0029663).
The applied reference has a common inventor/applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claims 1, 9 and 16, Lien et al. disclose an apparatus (for example figs. 1 – 6 and all related texts), comprising:
a memory array (fig. 2, para 0037) comprising a plurality of erase blocks (para 0037, “block erase” is performed to erase all cells of a block together as a group), wherein the plurality of erase blocks comprise a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block (referred to in para 0037 as different tier of the memory array) and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block (referred to as a different group of strings of a particular tier of the memory array, para 0037); and
a controller coupled to the memory array and configured to (see abstract, “controller” 108, fig. 1, for example. See also fig. 4 and all related texts):
determine that a sensing operation request is for data stored in the first group of memory cells on a first access line of the first group of access lines corresponding to the first erase block, wherein the first erase block is a partially programmed (referred to in abstract as corrective read operation of a target word line of a partially programmed block); and
apply a first sensing voltage to the first access line during a first sensing operation on the first access line (referred to in abstract as “applying a first corrective read voltage signal to the target word line during the corrective read operation”);
apply a first pass voltage to a number of programmed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation (referred to in abstract as “applying a second pass voltage to a first number of programmed word lines of the partially programmed block…”); and
apply a second pass voltage to a number of unprogrammed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation (referred to in abstract as “applying a first pass voltage to a number of unprogrammed word lines of the partially programmed block during the corrective read operation”).
Regarding claim 2, Lien et al. also disclose The apparatus of claim 1, wherein the partially programmed first erase block comprises the number of programmed word lines that include a number of programmed inner access lines (referred to in para 0006 as “inner word lines of a partially programmed block”. See also para 0049, 0050) and a programmed boundary access line (referred to in para 0054 as “boundary word line of a partially programmed block”) and wherein the first access line is one of the number of programmed inner access lines (referred to in para 0049 as “read operation on inner word line 305-…”).
Regarding claim 3, Lien et al. also disclose the apparatus of claim 2, wherein the partially programmed block comprises the number of unprogrammed word lines and wherein a first unprogrammed word line of the number of unprogrammed word lines is adjacent to the boundary word line (see para 0054 and 0055).
Regarding claims 4 and 17, Lien et al. also disclose the apparatus of claim 1, wherein a magnitude of the second pass voltage is less than a magnitude of the first pass voltage (see para 0014, 0052, 0058, etc… Note that the cited “first pass voltage” is referred to as the claimed “second pass voltage”; and the cited “second pass voltage” is referred to as the claimed “first pass voltage”).
Regarding claim 7, Lien et al. also disclose the apparatus of claim 1, wherein the plurality of erase blocks comprise a third group of memory cells coupled to a third group of access lines and corresponding toa third erase block (first group, second group, and third group of access lines are referred to as lines connected to different particular tiers of the memory array. See para 0037).
Allowable Subject Matter
Claims 5, 6, 8, 10 – 15, and 18 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the apparatus/method as set forth above, further comprising, in combination, the features and limitations additionally claimed at least in claims 5 and 8 (with respect to independent claim 1), 10 and 12 – 15 (with respect to independent claim 9), and 18 (with respect to independent claim 16).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
See also reference US Pat Pub 2024/0303187, figs. 4 and 7 and all related texts with regard to partial programmed block and pass voltages applied to programmed word lines and unprogrammed word lines.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 February 13, 2026