DETAILED ACTION
Claims 1-19 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application (18/601,598) under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copies of KR 10-2023-0111208 and KR 10-2024-0021374 were electronically retrieved by the USPTO on July 25, 2024.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 18/601,598 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. At this point in time, the examiner recommends --Reducing Peak Power Consumption in Processing Element Groups by Dividing a Source Clock into Clocks with Different Phases--.
The abstract of the disclosure is objected to because of the following informalities:
In line 3 of the page, “arranged for” is not understood. Is applicant trying to say that the first circuit is arranged as a plurality of PE groups?
In line 6 of the page, “respectively” is misspelled.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
On page 1, line 6, please insert the patent number for the parent application.
In paragraph 17, line 1, “disclosure” is misspelled.
In paragraph 17, line 2, “provided” is misspelled.
In paragraph 17, “respectively” is misspelled.
Paragraph 25 is grammatically incorrect and must be reworded. It appears that
--and-- should be inserted after the comma.
In paragraph 26, line 1, “disclosure” is misspelled.
In paragraph 26, line 1, “system” is misspelled.
In paragraph 26, “respectively” is misspelled.
In paragraph 32, line 1, “According” is misspelled.
In paragraph 32, applicant has misspelled “printed” as “princed” multiple times.
In paragraph 32, “respectively” is misspelled.
At the end of paragraph 419, the examiner is unfamiliar with the word “synthetized”. Does applicant mean --synthesized--? Also, remove the space before the final period.
In paragraph 425, replace “S1030” and “S1040” with --S1230-- and --S1240--, respectively.
Paragraphs 528, 536-537, and 543 include similar issues mentioned above.
Appropriate correction is required.
Drawings
FIGs.1, 2A, 4A, 6A-B, 7B-C, 8B-C, 11B-C, and 13-16C are objected to for failing to comply with 37 CFR 1.84(a)(1) and 37 CFR 1.84(L), which requires that all drawings be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, solid black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. The examiner asserts that the quality of FIG(s), which include fuzziness, noise, non-uniform lines, blur, slightly faded text, etc., is inadequate.
FIGs.2B, 10A, and 11B-C are objected to for failing to comply with 37 CFR 1.84(p)(3), which states that "Numbers, letters, and reference characters…should not be placed in the drawing so as to interfere with its comprehension. Therefore, they should not cross or mingle with the lines." For example:
In FIG.2B, the topmost “Convolution” incorrectly crosses a line.
In FIG.10A, “Source” is obscured by a symbol.
In FIGs.11B-C, “Clock source” overlaps a box.
FIGs.10A-C are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include reference number 2000, which is not mentioned in the description.
The drawings are objected to because of the following informalities:
In FIG.8A, replace “180” with --190--.
In FIG.11C, replace the 2nd “196a” in the chain with --196b--.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) and/or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections/Inquiries
Claim 1 is objected to because of the following informalities:
In line 3, replace “elements (PE)” with --element (PE)-- for improved grammar/readability.
Claim 8 is objected to because of the following informalities:
Lines 2-4 are grammatically incorrect and must be reworded. It appears that
--and-- should be inserted after the comma in line 3.
Claim 9 is objected to because of the following informalities:
In line 5, replace “elements (PE)” with --element (PE)-- for improved grammar/readability.
Claim 14 is objected to because of the following informalities:
In line 5, replace “elements (PE)” with --element (PE)-- for improved grammar/readability.
Claim 19 is objected to because of the following informalities:
Lines 2-4 are grammatically incorrect and must be reworded. It appears that
--and-- should be inserted after the comma in line 3.
Regarding claims 2, 10, and 15, applicant claims at least one of the plurality of clock signals is supplied to one of the plurality of PE groups (or NPUs). This language seems to encompass sending multiple clock signals to a single PE group (or NPU). The examiner has been unable to find such in the drawings, as each FIG appears to show each PE group/NPU receiving a single clock signal. Thus, if applicant does not actually intend to send multiple clocks to a single PE group/NPU, the examiner recommends inserting --each of-- prior to “at least one” in each of these claims. This way, if there are multiple clocks going through respective buffers, then each of these clocks will be supplied to one PE group/NPU.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 9, and 14 (and dependents) are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 11,954,586 in view of Gu (as cited below), and optionally, the examiner’s taking of Official Notice.
Claim 1 (and similarly each of claims 9 and 14) is mostly anticipated by claim 6 of ‘586. While claim 1 additionally includes a clock divider to generate the clock signals having different phases from the source/original clock signal, it would have been obvious to modify claim 6 of ‘586 to include Gu’s clock divider (FIG.3A, 282) since it includes simply delay components to achieve the different phases. This also provides staggering of activation timings, which reduce peak power consumption compared to if all components were clock at the same time.
Due to time constraints, the number of conflicting applications, and the large number of claims being compared, double patenting rejections for the dependent claims are not included in full herein. However, the examiner asserts that the dependent claims of the instant application do not set forth any limitation that is patentably distinct from the claims of ‘586, either alone, or as modified according to one of ordinary skill in the art, or according to the prior art cited below.
Claims 1, 9, and 14 (and dependents) are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 12,307,357 in view of Gu (as cited below), for similar reasoning that the same claims are not patentable over claim 6 of ‘586 (as detailed above).
Due to time constraints, the number of conflicting applications, and the large number of claims being compared, double patenting rejections for the dependent claims are not included in full herein. However, the examiner asserts that the dependent claims of the instant application do not set forth any limitation that is patentably distinct from the claims of ‘357, either alone, or as modified according to one of ordinary skill in the art, or according to the prior art cited below.
Claims 1, 9, and 14 (and dependents) are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,117,866 in view of Gu (as cited below), for similar reasoning that the same claims are not patentable over claim 6 of ‘586 (as detailed above).
Due to time constraints, the number of conflicting applications, and the large number of claims being compared, double patenting rejections for the dependent claims are not included in full herein. However, the examiner asserts that the dependent claims of the instant application do not set forth any limitation that is patentably distinct from the claims of ‘886, either alone, or as modified according to one of ordinary skill in the art, or according to the prior art cited below.
Claims 1, 9, and 14 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 or 2, or 9 or 10, or 14-15, of U.S. Patent No. 12,086,096. While claims 1-2 of ‘096 don’t explicitly recite the limitations of the last two paragraphs of the instant claims, the last two paragraph are essentially inherent side effects/properties of using the different phased clocks to clock the different PE groups (for reasons set forth in the prior art rejections below). In short, using different phase (staggered) clocks reduces simultaneous transistor switching which reduced peak power consumption compared to if the clocks were in phase.
Claims 2-8, 10-13, and 15-17 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 2-8, 10-13, and 15-17, of ‘096, which anticipate the instant claims.
Claims 1, 9, and 14 (and dependents) are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of copending Application No. 19/091,392 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other for similar reasoning that the claims are not patentable over ‘096/ Note that a phase shifter of ‘093 maps to the instant clock divider.
Due to time constraints, the number of conflicting applications, and the large number of claims being compared, double patenting rejections for the dependent claims are not included in full herein. However, the examiner asserts that the dependent claims of the instant application do not set forth any limitation that is patentably distinct from the claims of ‘392, either alone, or as modified according to one of ordinary skill in the art, or according to the prior art cited below.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7, and 9-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gu et al. (US 2021/0247797).
Referring to claim 1, Gu has taught a neural processing unit (NPU) (FIG.3A and paragraphs 33 and 36) comprising:
a plurality of processing elements (PE) groups (FIG.3A, PE groups CDM0, CDM1, …, CDM15) including a plurality of processing elements (FIG.3A, each group includes multiple PEs (PE0 through PE7)); and
a clock divider (FIG.3A, at least 282) configured to divide a source clock signal (FIG.3A, 284a) into a plurality of clock signals having different phases (FIG.3A and paragraphs 49-50, P0, P1, …, P27), the plurality of clock signals including a first clock signal and a second clock signal (any two of P0 through P27 are first and second clock signals),
wherein the first clock signal is provided to a first PE group among the plurality of PE groups, and the second clock signal is provided to a second PE group among the plurality of PE groups (from FIG.3A, note that each PE group has a corresponding multiplexer 295, which dynamically selects one of the clock signals. FIG.3C shows that a first PE group (CDM0) is provided initially with the P2 clock, and a second PE group (CDM1) is provided with the P3 clock. Also see FIGs.4A, 4C, and 4D, which show further examples of different PE groups being supplied with different clock signals),
wherein the plurality of clock signals having different phases are assigned to the plurality of PE groups such that peak power consumption caused by simultaneous switching of the plurality of PE groups is reduced (while this is not explicitly taught by Gu, the examiner asserts that this is an inherent side effect of using clocks having different phases. Fujitani (US 2018/0336932) is herein cited as extrinsic evidence in support of such an assertion (see FIG.9 and paragraph 63). Specifically, electronic systems are made up of many transistors, which switch on and off, when in operation, to generate signals and provide functionality and, thus, consume dynamic power. The transistors are generally understood to be in operation upon clock transitions, e.g. when a clock signal rises and/or falls. Thus, if all components use the same clock, then all components’ transistors will be switching on/off at the same time, thereby causing peak power consumption (because each transistor will be contributing a small amount of power consumption to an overall consumption at the same time). However, as taught by Fujitani, if transistor switching is staggered due to different clock phases being used, then fewer transistors switch on/off at once, thereby reducing peak power consumption in favor of more level but lower power consumption. In short, using the same clock for everything would generally result in swings between peak power consumption and minimum power consumption, while different clock phases would generally result in non-peak, but more consistent/level power consumption), and
wherein phase differences among the plurality of clock signals are configured such that activation timings of the plurality of PE groups are staggered, thereby reducing peak power consumption (again, see the reasoning given above. If components in the system are not all switching on at once, then peak power consumption is reduced. The use of clock staggering in Gu’s FIG.4A, for instance, would reduce peak power consumption, which would instead be experienced if all of the clock transitions perfectly lined up).
Referring to claim 2, Gu has taught the NPU of claim 1 wherein at least one of the plurality of clock signals is supplied to one of the plurality of PE groups after passing through at least one clock buffer arranged for peak power reduction (see FIG.3B, clock buffer 210a and paragraph 51).
Referring to claim 3, Gu has taught the NPU of wherein a frequency of the plurality of clock signals is determined based on a number of the plurality of PE groups (the frequency of clock 284a (and, thus, each of clocks P0-P27) is determined based on the design of the system being clocked, including the number of PE groups).
Referring to claim 4, Gu has taught the NPU of wherein a frequency of the plurality of clock signals is determined as a frequency of the source clock signal divided by a number of the plurality of PE groups (in FIG.3A, unit 282 does not change the frequency of the source clock 284a. Thus, the output frequency of the clock signals is determined to be the frequency of the source clock divided by delay elements 282a-x to generate the clock signals).
Referring to claim 5, Gu has taught the NPU of claim 1 wherein the second clock signal is delayed in phase with respect to the first clock signal (from FIG.3A, each clock signal Px is delayed in phase with respect to clock signal Px-1).
Referring to claim 7, Gu has taught the NPU of claim 1 wherein the clock divider includes a plurality of delay cells (FIG.3A, cells 282a through 282x) and a multiplexer connected in parallel with the plurality of delay cells (see mux 295a, which receives each Px clock from each of the delay cells and is thus connected in parallel with the delay cells).
Referring to claim 9, Gu has taught a system-on-chip (SoC) (FIG.2A, “Chip Top-level Architecture”, meaning the system in on a chip) comprising:
a semi-conductor substrate (such a substrate is required to implement the circuitry of the system);
a plurality of processing elements (PE) groups (FIG.3A, PE groups CDM0, CDM1, …, CDM15) including a plurality of processing elements (FIG.3A, each group includes multiple PEs (PE0 through PE7)); and
a clock divider (FIG.3A, at least 282) arranged on the semi-conductor substrate, configured to divide a source clock signal (FIG.3A, 284a) into a plurality of clock signals having different phases (FIG.3A and paragraphs 49-50, P0, P1, …, P27), the plurality of clock signals including a first clock signal and a second clock signal (any two of P0 through P27 are first and second clock signals),
wherein the first clock signal is provided to a first neural processing unit (NPU) among a plurality of NPUs, and the second clock signal is provided to a second NPU among the plurality of NPUs (from FIG.3A, note that each PE group has a corresponding multiplexer 295, which dynamically selects one of the clock signals. FIG.3C shows that a first PE group (CDM0) is provided initially with the P2 clock, and a second PE group (CDM1) is provided with the P3 clock. Also see FIGs.4A, 4C, and 4D, which show further examples of different PE groups being supplied with different clock signals. Note that each PE group is an NPU to perform neural network operations (paragraphs 33 and 36)),
wherein the plurality of clock signals having different phases are assigned to the plurality of NPUs such that peak power consumption caused by simultaneous switching of the plurality of NPUs is reduced (while this is not explicitly taught by Gu, the examiner asserts that this is an inherent side effect of using clocks having different phases. Fujitani is again cited as extrinsic evidence in support of such an assertion (see FIG.9 and paragraph 63). Specifically, electronic systems are made up of many transistors, which switch on and off, when in operation, to generate signals and provide functionality and, thus, consume dynamic power. The transistors are generally understood to be in operation upon clock transitions, e.g. when a clock signal rises and/or falls. Thus, if all components use the same clock, then all components’ transistors will be switching on/off at the same time, thereby causing peak power consumption (because each transistor will be contributing a small amount of power consumption to an overall consumption at the same time). However, as taught by Fujitani, if transistor switching is staggered due to different clock phases being used, then fewer transistors switch on/off at once, thereby reducing peak power consumption in favor of more level but lower power consumption. In short, using the same clock for everything would generally result in swings between peak power consumption and minimum power consumption, while different clock phases would generally result in non-peak, but more consistent/level power consumption), and
wherein phase differences among the plurality of clock signals are configured such that activation timings of the plurality of NPUs are staggered, thereby reducing peak power consumption (again, see the reasoning given above. If components in the system are not all switching on at once, then peak power consumption is reduced. The use of clock staggering in Gu’s FIG.4A, for instance, would reduce peak power consumption, which would instead be experienced if all of the clock transitions perfectly lined up).
Claims 10-13 are rejected for similar reasoning as claims 2-5, respectively.
Referring to claim 14, Gu has taught an electronic device comprising:
a printed circuit board (from FIG.2A, the architecture comprises a chip, which is a printed circuit board);
a plurality of neural processing units (NPUs) including a plurality of processing elements (PE) groups (FIG.3A, one NPU would be CDM0, which includes a group of PEs therein. Another NPU would be CDM1, which includes a group of PEs therein) including a plurality of processing elements (FIG.3A, each PE group includes multiple PEs (PE0 through PE7)), arranged on the printed circuit board (all components are on the chip/board); and
a clock divider (FIG.3A, at least 282) arranged on the printed circuit board, configured to divide a source clock signal (FIG.3A, 284a) into a plurality of clock signals having different phases (FIG.3A and paragraphs 49-50, P0, P1, …, P27), the plurality of clock signals including a first clock signal and a second clock signal (any two of P0 through P27 are first and second clock signals),
wherein the first clock signal is provided to a first NPU among the plurality of NPUs, and the second clock signal is provided to a second NPU among the plurality of NPUs (from FIG.3A, note that each PE group has a corresponding multiplexer 295, which dynamically selects one of the clock signals. FIG.3C shows that a first PE group (CDM0) is provided initially with the P2 clock, and a second PE group (CDM1) is provided with the P3 clock. Also see FIGs.4A, 4C, and 4D, which show further examples of different PE groups being supplied with different clock signals. Note that each PE group is an NPU to perform neural network operations (paragraphs 33 and 36)),
wherein the plurality of clock signals having different phases are assigned to the plurality of NPUs such that peak power consumption caused by simultaneous switching of the plurality of NPUs is reduced (while this is not explicitly taught by Gu, the examiner asserts that this is an inherent side effect of using clocks having different phases. Fujitani is again cited as extrinsic evidence in support of such an assertion (see FIG.9 and paragraph 63). Specifically, electronic systems are made up of many transistors, which switch on and off, when in operation, to generate signals and provide functionality and, thus, consume dynamic power. The transistors are generally understood to be in operation upon clock transitions, e.g. when a clock signal rises and/or falls. Thus, if all components use the same clock, then all components’ transistors will be switching on/off at the same time, thereby causing peak power consumption (because each transistor will be contributing a small amount of power consumption to an overall consumption at the same time). However, as taught by Fujitani, if transistor switching is staggered due to different clock phases being used, then fewer transistors switch on/off at once, thereby reducing peak power consumption in favor of more level but lower power consumption. In short, using the same clock for everything would generally result in swings between peak power consumption and minimum power consumption, while different clock phases would generally result in non-peak, but more consistent/level power consumption), and
wherein phase differences among the plurality of clock signals are configured such that activation timings of the plurality of NPUs are staggered, thereby reducing peak power consumption (again, see the reasoning given above. If components in the system are not all switching on at once, then peak power consumption is reduced. The use of clock staggering in Gu’s FIG.4A, for instance, would reduce peak power consumption, which would instead be experienced if all of the clock transitions perfectly lined up).
Claims 15-18 are rejected for similar reasoning as claims 2, 4-5, and 7, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 8, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gu in view of the examiner’s taking of Official Notice.
Referring to claim 6, Gu has taught the NPU of claim 1 wherein the clock divider includes a plurality of delay elements for delaying the source clock signal (FIG.3A, elements 282a-x), a multiplexer connected in parallel with the plurality of delay elements (see mux 295a, which receives each Px clock from each of the delay cells and is thus connected in parallel with the delay cells).
Gu has not taught that the delay elements are flip-flops. However, Official Notice is
taken that flip-flops were well known in the art, before applicant’s invention, as foundational computing system components that can be used to implement delay. A flip-flip is a simple, common, inexpensive component that is readily-available. For these reasons, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify delay elements 282a-x of Gu to be flip-flops.
Gu has also not taught a divider for dividing a frequency of an output signal from the multiplexer. However, Official Notice is taken that a clock frequency divider was well known in the art before applicant’s invention. Such a divider slows a clock down, which slows components (and internal transistor switching down), which means power consumption is reduced over time. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gu to include a divider for dividing a frequency of an output signal from the multiplexer. One would be further motivated to put a diver in this location to flexibly control the clock for any given PE group. In other words, there could be a clock divider at the output of each multiplexer in FIG.3A to flexibly control clock speed of each PE group.
Referring to claim 8, Gu has taught the NPU of claim 1 wherein the clock divider includes a divider (FIG.3A, at least 282 and at least one multiplexer 295 form the divider) coupled to the source clock signal (FIG.3A, 282 is coupled to source clock 284a) to divide a frequency of the source clock signal (the source clock has a frequency and the clock is divided into multiple clock signals; thus, it can be said that the source frequency is divided (the examiner notes the breadth of the claim, specifically that the clock division is not claimed to lower the frequency), a first component coupled to an output of the divider (FIG.3B, the output of the multiplexer 295a, which may be considered part of the divider, is coupled to a latching component to the right of the adder), and wherein each of the divider and the component is configured to be operated by receiving a frequency of the source clock signal (from FIG.3A, PD & Loop 283, which is part of the divider, receives the source clock signal CLK. Furthermore, when 295A, which is also part of the divider, selects P0 (which is also the source clock signal), the source clock also operates the component referenced in FIG.3B).
While Gu has not taught that the referenced component in FIG.3B is a D-type flip-
flop, Official Notice is taken that a D-flip-flop was well known in the art before applicant’s invention. Further, a D-flip-flop is known to operate as shown in FIG.3B, where an input would be latched in from the adder when clocked and the provide that output on a “Q” output, as is known. As similarly stated above, a D-flip-flip is a simple, common, inexpensive component that is readily-available. For these reasons, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the component to the right of the adder in FIG.3B of Gu to be a D-flip-flop.
Claim 19 is rejected for similar reasoning as claim 8.
Response to Arguments
On page 9 of applicant’s response, applicant argues that Gu performs phase selection to satisfy timing constraints, accommodate process-voltage-temperature variations, and ensure synchronization between clock domains, but does not teach assigning different phase clocks to reduce peak power by simultaneous switching, or staggering activation timings of PE groups to distribute peak power over time.
The examiner asserts that Gu has taught the staggering since different PE groups can use different phase clocks, and the limitations related to peak power are simply side effects of such an implementation. That is, if all clocks were of the same phase in Gu, then more transistors would be simultaneous switching and consuming power, thereby realizing a peak power consumption. However, staggering clock transitions means fewer switching at once and, thus, less power consumption. In other words, peak consumption would be less with the staggering taught by Gu as opposed to if non-staggering were performed in Gu.
All arguments with respect to Narayanaswamy are moot since the reference is no longer relied upon in a rejection due to applicant’s amendments that no longer required that clock signals generated from the source clock signal have a lower frequency from the source clock.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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