DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
1. The information disclosure statements (IDS) submitted on 7/25/2024 and is in compliance with the provisions of 37 CFR 1.97. According, the information disclosure statement is being considered by the Examiner. Election/Restrictions
2. Applicant elected, with traverse, of Group I (claims 1-10 and 17-20) as readable on the elected invention, in the reply filed on 3/20/2026 is acknowledged. Claims 11-16 of Group II are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. The traversal is on the ground(s) that “if the search and examination of an entire application can be made without serious burden, the Examiner must examine it on the merits. M.P.E.P. §803. Additionally, the Restriction Requirement and/or the Election of Species are traversed on the basis that a Restriction Requirement and Election of Species are optional. M.P.E.P. §806”. This is not found persuasive because the invention of Group I claims a product, while the invention of Group II claims a method of performance steps of testing the product. The claim limitations of Group I may be performed with other methods of testing than the ones claimed in Group II (claims 11-16) that do not require performance steps of focusing light from a first laser source onto a first oxide portion of a memory die, wherein: the first oxide portion is in contact with a first via and a first metal line; and the focusing of the light from the first laser source onto the first oxide portion causes the first oxide portion to change from an insulator to a conductor; and focusing light from a second laser source onto a second oxide portion of a memory die, the focusing of the light from second laser source onto the second oxide portion causes the second oxide portion to change from an insulator to a conductor…. Thus, there is a serious search and examination burden to search for structures as claimed for Group I versus the method of testing as claimed for Group II. The requirement is still deemed proper and is therefore made FINAL
Examiner Notes
3. Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al. (US. Pub. 2005/0030055; hereinafter “Tran”) in view of Lin et al. (US. Pub. 2011/0026297; hereinafter “Lin”).
Regarding claim 1, Tran discloses a memory die (a memory die 10 on a wafer 116 in Fig. 5), comprising: a plurality of metal lines (a plurality of metal lines 49, 49b, 51, 51b. See annotated Fig. 4); a cantilever (a metal portion 46 is considered as a cantilever, interpreted in light of Figs. 3C-3D in the instant application) in contact with at least a first metal line (a metal line 51) and a second metal line (a metal line 51b, see annotated Fig. 4) of the plurality of metal lines; a circuit (26-27) comprising at least one transistor (a transistor level 27) or at least one diode in contact with at least the first metal line of the plurality of metal lines (Fig. 4 shows that the transistor level 27 electrically contacted with the metal line 51); and a diode or transistor (a driver circuit 47 comprises ESD circuitry or buffering circuitry which includes diodes. See [0020]) in contact with at least the second metal line of the plurality of metal lines (the driver circuit 47 electrically contacted with the metal line 51b, see Fig. 4); wherein: an end of the cantilever is in contact with the first metal line through a first via as shown in Fig. 4, one end portion of the cantilever 46 is contacted with the metal line 51 through a via 45); a portion of the cantilever is in contact with the second metal line through a second via an opposite end portion of the cantilever 46 is contacted with the metal line 51b through a via 45b, see annotated Fig. 4); and the diode or the transistor (47) is located at a distance from the circuit including other transistors and other diodes than the at least one transistor or the at least one diode (Fig. 4 shows that the driver 47 is located a distance from the transistor level 27).
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Tran does not disclose an oxide portion that is used for connecting between the first metal line and the first via, and between the second metal line and the second via.
Lin discloses, in Figs. 1A-1B, using an oxidation portion (110) for coupling between a conductive via (130) and an electrode (120).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ connections between metal lines and conductive vias in the integrated circuit of Tran by using an oxidation portion for coupling between the first metal line and the first via and between the second metal line and the second via as taught by Lin for purpose of providing the metallic oxide portion in connections, which provided high stability, cost-effectiveness, thermal resistance, and tunable semiconducting properties.
Regarding claim 2, Tran and Lin disclose the memory die of claim 1, Tran in view of Lin further teaches wherein the end of the cantilever (the end of cantilever 46 of Tran in Fig. 4) is in direct contact with the first via (the first via 45 of Tran), the first via (45) is in direct contact with the first oxide portion (the oxidation portion 110 of Lin), and the first oxide portion is in direct contact with the first metal line (the oxidation 110 of Lin is directly contacted between the first via 45 and the first metal line 51 of Tran).
Regarding claim 3, Tran and Lin disclose the memory die of claim 2, Tran in view of Lin further teaches wherein the portion of the cantilever (the portion of cantilever 46 of Tran in Fig. 4) is in direct contact with the second via (the second via 45b of Tran), the second via is in direct contact with the second oxide portion (the oxidation portion 110 of Lin in Figs. 1A-B), and the second oxide portion is in direct contact with the second metal line (the oxidation 110 of Lin is directly contacted between the second via 45b and the second metal line 51b of Tran).
Regarding claim 4, Tran and Lin disclose the memory die of claim 1, Tran in view of Lin further teaches wherein the end of the cantilever (the end of cantilever 46 of Tran in Fig. 4) is in direct contact with the first oxide portion(the oxidation portion 110 of Lin in Figs. 1A-B), the first oxide portion is in direct contact with the first via, and the first via is in direct contact with the first metal line (the oxidation 110 of Lin is directly contacted between the first via 45 and the first metal line 51 of Tran).
Regarding claim 5, Tran and Lin disclose the memory die of claim 4, Tran in view of Lin further teaches wherein the portion of the cantilever (the portion of cantilever 46 of Tran in Fig. 4) is in direct contact with the second oxide portion (the oxidation portion 110 of Lin), the second oxide portion is in direct contact with the second via, and the second via is in direct contact with the second metal line (the oxidation 110 of Lin is directly contacted between the second via 45b and the second metal line 51b of Tran).
Regarding claims 6-7, Tran and Lin disclose the memory die of claim 1, except for explicitly specifying that wherein the first metal line is a supply probe pad or a ground point.
However using the first metal line for serving a particular function such as a supply probe pad or a ground point, it would simply be a matter of inventor design choice.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the memory die of Tran and Lin by having the first metal line is a supply probe pad or a ground point, in order to meet the system design and specification requirement.
Regarding claims 8-9, Tran and Lin disclose the memory die of claim 1, wherein the second metal line is a power supply voltage or a ground probe pad.
However using the second metal line for serving a particular function such as a power supply voltage or a ground probe pad, it would simply be a matter of inventor design choice.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the memory die of Tran and Lin by having the second metal line is a power supply voltage or a ground probe pad, in order to meet the system design and specification requirement.
Regarding claim 10, Tran and Lin disclose the memory die of claim 1, Tran in view of Lin further teaches comprising a third metal line (the metal line 51b in Fig. 3 of Tran ) in contact with an additional end of the cantilever opposite the end (an end of the cantilever 46 coupled to the driver 47 in Fig. 3 of Tran) through a third via and a third oxide portion (the oxidation 110 of Lin is directly contacted between the third via 45b and the third metal line 51b of Tran).
Regarding claim 17, Tran discloses an apparatus (Fig. 1), comprising: a memory die including a group of memory cells (a memory die 10 on a wafer 116, in Fig. 5, including memory cells. See claims 18-21); wherein the memory die (10) comprises: a first metal line (a metal line 32 in Fig. 3), a second metal line (a metal line 51 in Fig. 3), and a third metal line (51b in Fig. 3); and a cantilever (a metal portion 46 is considered as a cantilever, interpreted in light of Figs. 3C-3D in the instant application) in contact with the first metal line (32), the second metal line (51), and the third metal line (51b in annotated Fig. 3), wherein: a first end of the cantilever (an end portion of the cantilever 46) is in contact with the first metal line (32) through a first via (a metal via 29); a middle portion of the cantilever (46) is in contact with the second metal line (51) through a second via (a metal via 45); and a second end (an opposite end portion of the cantilever 46), opposite the first end, of the cantilever (46) is in contact with the third metal line (51b) through a third via (a metal via 45b).
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Tran does not disclose an oxide portion that is used for connecting between the first metal line and the first via, between the second metal line and the second via, and between the second metal line and the second via.
Lin discloses, in Figs. 1A-1B, using an oxide portion (110) for coupling between a conductive via (130) and an electrode (120).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ connections between metal lines and conductive vias in the integrated circuit of Tran by using an oxidation portion for coupling between the first metal line and the first via, between the second metal line and the second via, and between the third metal line and the third via as taught by Lin for purpose of providing the metallic oxide portion in connections, which provided high stability, cost-effectiveness, thermal resistance, and tunable semiconducting properties.
6. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Tran in view of Lin and further in view of Johnson et al. (US. Pub. 2024/0194287; hereinafter “Johnson”).
Regarding claim 18, Tran and Lin disclose the apparatus of claim 17, Tran further teaches comprising a plurality of memory dies (a plurality of memory dies 10 in Fig. 5) and each including a group of memory cells (see claims 18-21), and the memory die is one of the plurality of memory dies (10), except for explicitly specifying a plurality of memory dies arranged in a stack.
John discloses an apparatus (100 in Fig. 1 or 200 in Fig. 2) comprising a plurality of memory dies (160in Fig. 1 or 240 in Fig. 2) arranged in a stack (dies 160 are arranged in a stack, see [0025], or dies 240 and die 205 are arranged in a stack, see [0034]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the memory system of Tran and Lin by having a plurality of memory dies arranged in a stack, as taught by John for purpose of providing the apparatus improves a manufacturing yield rate or storage rating for a semiconductor system, increases overall product yield, reduces an amount of overall memory capacity.
7. Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Tran in view of Lin and further in view of Hong et al. (US. Pub. 2011/0158022; hereinafter “Hong”).
Regarding claim 19, Tran and Lin disclose the apparatus of claim 17, except for explicitly specifying further comprising a DC power supply connected in parallel with two switches each connected to at least one of the first metal line, the second metal line, and the third metal line.
Hong discloses, in Fig. 2, a memory device comprising a DC power supply (VDD power supply in Fig. 2) connected in parallel with two switches (power switches P10-12) each connected to at least one of the first metal line (a metal line ML1), the second metal line (a metal line ML2), and the third metal line (a metal line ML3).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the memory system of Tran and Lin by having a DC power supply connected in parallel with two switches each connected to at least one of the first metal line, the second metal line, and the third metal line, as taught by Hong for purpose of driving the voltage line to the external voltage and another voltage line to the ground voltage, so that the sense amplifier is driven in such a state that noise components of the voltage lines are removed.
8. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tran in view of Lin and further in view of Mochizuki et al. (US. Pat. 5680039; hereinafter “Mochizuki”).
Regarding claim 20, Tran and Lin disclose the apparatus of claim 17, except for explicitly specifying further comprising a C-V meter connected in parallel with two switches each connected to at least one of the first metal line, the second metal line, and the third metal line.
Mochizuki discloses, in Fig. 2, a C-V meter (a voltage and current measurement unit SMU 6) connected in parallel with two switches (24, 28) each connected to at least one of the first metal line, the second metal line, and the third metal line (measurements are performed with metal lines 8, 32, and 34 in contact with the device under test 50).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the memory system of Tran and Lin by having a measurement meter connected in parallel with two switches each connected to at least one of the first metal line, the second metal line, and the third metal line, as taught by Mochizuki for purpose of driving the voltage line to the external voltage and another voltage line to the ground voltage, so that the sense amplifier is driven in such a state that noise components of the voltage lines are removed.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANG LE whose telephone number is (571)272-9349. The examiner can normally be reached on Monday thru Friday 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THANG X LE/Primary Examiner, Art Unit 2858
5/5/2026
Prosecution Insights