DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a plurality of third nanostructures, and a plurality of fourth nanostructures” of claim 1, “separating the plurality of third nanostructures and the plurality of fourth nanostructures with the dielectric fin structure; forming a third gate structure wrapping around each of the third nanostructures except for a sidewall that is in contact with the dielectric fin structure; forming a fourth gate structure wrapping around each of the fourth nanostructures except for a sidewall that is in contact with the dielectric fin structure, wherein the third and fourth gate structures extend along the second lateral direction; and forming a second interconnect structure coupled to both of the third gate structure and fourth gate structure” of claim 2; “the plurality of third nanostructures each extend from a corresponding one of the plurality of fourth nanostructures along the second lateral direction, the method further comprising: forming a fifth gate structure wrapping around a combination of each of the third nanostructures and the corresponding fourth nanostructures; and forming a third interconnect structure coupled to the fifth gate structure” of claim 3; “a plurality of third nanostructures extending along the first lateral direction” of claim 10, “the plurality of third nanostructures each are formed to extend from a corresponding one of the plurality of second nanostructures along the second lateral direction, and wherein the second gate structure is formed to straddle the plurality of third nanostructures” of claim 11, “the dielectric fin structure is formed immediately next to a third sidewall of each of the plurality of third nanostructures along the second lateral direction, and wherein the third gate structure is formed to wrap around each of the plurality of third nanostructures except for the third sidewalls” of claim 13 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the first lateral direction" in lines 5-6. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of this Action, the above limitation of claim 1 will be interpreted and examined as --a first lateral direction--.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 4-11, 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (US Pub. 20210391222)
Regarding claim 4, Xie et al. discloses in Fig. 1, Fig. 17A, Fig. 17B a method of fabricating a memory device, comprising:
forming a plurality of first nanostructures extending along a first lateral direction [X];
forming a plurality of second nanostructures extending along the first lateral direction [X];
forming a dielectric fin structure [420] disposed immediately next to a first sidewall of each of the plurality of first nanostructures along a second lateral direction [Y] perpendicular to the first lateral direction [X];
forming a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewalls; and
forming a second gate structure straddling the plurality of second nanostructures.
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Regarding claim 5-11, Xie et al. discloses in Fig. 1, Fig. 17B
wherein the dielectric fin structure [402] extends along the first lateral direction [X];
wherein the first and second gate structures each are formed to extend along the second lateral direction [Y];
wherein the dielectric fin structure [402] is formed immediately next to a second sidewall of each of the plurality of second nanostructures along the second lateral direction [Y];
wherein the second gate structure is formed to wrap around each of the plurality of second nanostructures except for the second sidewalls;
wherein the second gate structure is formed to wrap around each of the plurality of second nanostructures;
forming a plurality of third nanostructures extending along the first lateral direction [X];
wherein the plurality of third nanostructures each are formed to extend from a corresponding one of the plurality of second nanostructures along the second lateral direction [Y], and wherein the second gate structure is formed to straddle the plurality of third nanostructures.
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Regarding claim 14, the limitation “wherein the plurality of first nanostructures and the first gate structure at least form, in part, a programming transistor of an anti-fuse memory cell, and the plurality of second nanostructures and the second gate structure at least form, in part, a reading transistor of the anti-fuse memory cell” direct to intended use of the claimed structure comprising the plurality of first nanostructures, the first gate structure, the plurality of second nanostructures and the second gate structure. A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In this case, Xie et al. discloses the claimed structure and Xie’s structure is capable of performing the intended use, thus it meets the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US Pub. 20210391222) in view of Liaw (US Pub. 20200105761)
Regarding claims 1-2, Xie et al. discloses in Fig. 1, Fig. 17A, Fig. 17B a method of fabricating a memory device, comprising:
forming a plurality of first nanostructures, a plurality of second nanostructures, a plurality of third nanostructures, and a plurality of fourth nanostructures;
separating the plurality of first nanostructures and the plurality of second nanostructures with a dielectric fin structure [402], wherein the dielectric structure [402] also extends along a first lateral direction [X];
forming a first gate structure [gate of first PFET stack] wrapping around each of the first nanostructures except for a sidewall that is in contact with the dielectric fin structure [50];
forming a second gate structure [gate of first NFET stack] wrapping around each of the second nanostructures except for a sidewall that is in contact with the dielectric fin structure [402], wherein the first and second gate structures extend along a second lateral direction [Y] perpendicular to the first lateral direction [X];
separating the plurality of third nanostructures and the plurality of fourth nanostructures with the dielectric fin structure [402];
forming a third gate structure wrapping around each of the third nanostructures except for a sidewall that is in contact with the dielectric fin structure [402];
forming a fourth gate structure wrapping around each of the fourth nanostructures except for a sidewall that is in contact with the dielectric fin structure [402],
wherein the third and fourth gate structures extend along the second lateral direction [Y].
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Xie et al. fails to disclose
forming a first interconnect structure coupled to one of the first gate structure or second gate structure;
forming a second interconnect structure coupled to both of the third gate structure and fourth gate structure.
Liaw discloses in Fig. 6A, Fig. 6B, paragraph [0073]-[0074]
forming a first interconnect structure [gate vias] coupled to one of the first gate structure or second gate structure;
forming a second interconnect structure [gate vias] coupled to both of the third gate structure and fourth gate structure.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Liaw into the method of Xie et al. to include forming a first interconnect structure coupled to one of the first gate structure or second gate structure; forming a second interconnect structure coupled to both of the third gate structure and fourth gate structure. The ordinary artisan would have been motivated to modify Xie et al. in the above manner for the purpose of providing an interconnect to a multilayer interconnect (MLI) feature disposed over substrate [paragraph [0056], [0073] of Liaw]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 3, Xie et al. discloses in Fig. 1, Fig. 17A, Fig. 17B
wherein the plurality of third nanostructures each extend from a corresponding one of the plurality of fourth nanostructures along the second lateral direction [Y],
the method further comprising:
forming a fifth gate structure wrapping around a combination of each of the third nanostructures and the corresponding fourth nanostructures.
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Liaw discloses in Fig. 6A, Fig. 6B, paragraph [0073]-[0074]
forming a third interconnect structure coupled to the fifth gate structure.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Liaw into the method of Xie et al. to include forming a third interconnect structure coupled to the fifth gate structure. The ordinary artisan would have been motivated to modify Xie et al. in the above manner for the purpose of providing an interconnect of the fifth gate structure to a multilayer interconnect (MLI) feature disposed over substrate [paragraph [0056], [0073] of Liaw]. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US Pub. 20210391222) as applied to claim 10 above in view of Chen et al. (US Pub. 20220028899).
Regarding claims 12-13, Xie et al. discloses in Fig. 1, Fig. 17B
forming a third gate structure aligned with the second gate structure along the second lateral direction;
wherein the dielectric fin structure [402] is formed immediately next to a third sidewall of each of the plurality of third nanostructures along the second lateral direction [Y], and wherein the third gate structure is formed to wrap around each of the plurality of third nanostructures except for the third sidewalls.
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the third gate structure separated apart from the second gate structure with the dielectric fin structure.
Chen et al. discloses in Fig. 9, paragraph [0095], [0103]-[0104], [0115]
the third gate structure [224] separated apart from the second gate structure [223] with the dielectric fin structure [213].
Chen et al. suggests that one gate structure is in contacted with another gate structure or one gate structure is separated from another gate structure.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen et al. into the method of Xie et al. to include the third gate structure separated apart from the second gate structure with the dielectric fin structure. The ordinary artisan would have been motivated to modify Xie et al. in the above manner for the purpose of isolating the third gate structure from the second gate structure to independently control voltages applied to the third gate structure and the second gate structure [paragraph [0115] of Chen et al.].
Claims 15-16, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2013007376) in view of Xie et al. (US Pub. 20210391222).
Regarding claims 15, 16 and 20, Kim et al. discloses in Fig. 3-Fig. 5, Fig. 8-Fig. 9, a method of fabricating a memory device, comprising:
forming a plurality of memory cells [OTP memory cells included in cell array 140], each of which includes a first programming transistor and a first reading transistor coupled to each other in series, and a second programming transistor and a second reading transistor coupled to each other in series [paragraph [0036]].
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wherein a first channel structure of the first programming transistor is formed to have a first sidewall, and a second channel structure of the second programming transistor is formed to have a second sidewall facing the first sidewall; and
wherein the first sidewall and second sidewall are each formed in contact with a dielectric fin structure;
wherein a third channel structure of the first reading transistor is formed to have a third sidewall, and a fourth channel structure of the second reading transistor is formed to have a fourth sidewall facing the third sidewall, and wherein the third sidewall and fourth sidewall are each formed in contact with the dielectric fin structure;
wherein each of the first channel structure and second channel structure is formed to include a plurality of nanostructure vertically spaced apart from one another.
Xie et al. discloses in Fig. 1, Fig. 17B
wherein a first channel structure of a first transistor is formed to have a first sidewall, and a second channel structure of a second transistor is formed to have a second sidewall facing the first sidewall; and
wherein the first sidewall and second sidewall are each formed in contact with a dielectric fin structure;
wherein a third channel structure of a third transistor is formed to have a third sidewall, and a fourth channel structure of a fourth transistor is formed to have a fourth sidewall facing the third sidewall, and wherein the third sidewall and fourth sidewall are each formed in contact with the dielectric fin structure;
wherein each of the first channel structure and second channel structure is formed to include a plurality of nanostructure vertically spaced apart from one another.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Xie et al. into the method of Kim et al. to include wherein a first channel structure of the first programming transistor is formed to have a first sidewall, and a second channel structure of the second programming transistor is formed to have a second sidewall facing the first sidewall; and wherein the first sidewall and second sidewall are each formed in contact with a dielectric fin structure; wherein a third channel structure of the first reading transistor is formed to have a third sidewall, and a fourth channel structure of the second reading transistor is formed to have a fourth sidewall facing the third sidewall, and wherein the third sidewall and fourth sidewall are each formed in contact with the dielectric fin structure. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of forming a memory device with fork nanosheet field-effect transistor (FET) devices that offer further scaling opportunities [paragraph [0002] of Kim et al.].
Regarding claims 18-19, Kim et al. discloses in Fig. 8-Fig. 9
forming a plurality of programming word lines [WLP], one of which is operatively coupled to one of a gate [G12] of the first programming transistor [M12] or a [G15] gate of the second programming transistor [M15]; and
forming a plurality of reading word lines [WLR], one of which is operatively coupled to both of a gate [G13] of the first reading transistor [M13] and a gate [G16] of the second reading transistor [M16];
forming a plurality of bit lines [BL], one of which is operatively coupled to both of a source/drain of the first reading transistor [M13] and a source/drain of the second reading transistor [M16].
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Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US Pub. 2013007376) in view of Xie et al. (US Pub. 20210391222) as applied to claim 15 above and further in view of Chen et al. (US Pub. 20140098591).
Regarding claim 17, Kim et al. fails to disclose
wherein the first reading transistor and second reading transistor are formed to share a common fifth channel structure.
Chen et al. discloses in Fig. 1A, Fig. 1C, paragraph [0050]-[0055]
wherein the first reading transistor and second reading transistor are formed to share a common fifth channel structure [118/130].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Chen et al. into the method of Kim et al. to include wherein the first reading transistor and second reading transistor are formed to share a common fifth channel structure. The ordinary artisan would have been motivated to modify Kim et al. in the above manner for the purpose of enabling to determine the state of the memory cell in one attempt [paragraph [0054]-[0055] of Chen et al.].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SOPHIA T NGUYEN/Primary Examiner, Art Unit 2893
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