Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to remarks and amendments received 04/21/2026.
Claims 1, 7, 9, and 13 are amended.
Claim 12 is cancelled.
Response to Arguments
Applicant’s arguments, filed 04/21/2026, with respect to the rejection of amended claims 3 – 11 and 13 – 20, under 35 U.S.C. 112(b), have been fully considered and are persuasive. The rejection of amended claims 3 – 20, under 35 U.S.C. 112(b), has been withdrawn.
Applicant's arguments filed 04/21/2026, regarding the rejection of amended claims 1 – 3, 6 – 9, and 14 – 20, under 35 U.S.C. 102(a)(1), and amended claims 4, 5, 10, 11, and 13, under 35 U.S.C. 103 have been fully considered but they are not persuasive.
Regarding amended claim 1, as representative, Applicant argues the prior art of record fails to disclose, teach, or reasonably suggest in combination the limitation “initialize the memory with a deterministic pattern and a pattern size congruent to a size of the memory data word”.
Specifically, applicant argues “Chen discloses providing stress data (and inverse stress data) to memory arrays. However, there is no disclosure in Chen of a deterministic pattern with a congruent size to the memory data word. Instead, Chen generically discloses "stress data", of indeterminate size, to set each memory element into a first state. That is, Chen does not disclose "a pattern size congruent to a size of the memory data word" as recited in the pending claims”. The Examiner disagrees.
The Examiner asserts the “stress data”/ “stress vector” disclosed by Chen is the same number of bits as a data word, as disclosed by applicant (paragraph 0035). Chen discloses “stress data”/ “stress vector” as potentially “either all 0s or all 1s” (paragraph 0042). The Examiner asserts independent of the size of a data word, a pattern disclosed as all 0s or all 1s will be the same number of bits (congruent) as the data word when all bits of the data word are written. Chen additionally discloses writing to the memory array as well understood in the art of MBIST testing (paragraph 0003). Finally, Chen discloses the multiple memory arrays are defined by word size (paragraph 0016, 64x32 bits, 256x512 bits).
The Examiner asserts, in combination the disclosure of Chen of: a pattern which is capable of being any bit length (paragraph 0042) and a memory with a defined word size (paragraph 0016), the “stress data”/ “stress vector” would be congruent (same number of bit) with the word length of the memory arrays.
And in light of the argument above the rejection of the claims is maintained.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim 7
means for initializing a current memory address in a plurality of memories to a memory address using a plurality of shared built-in self-test (BIST) resources in a computing system;
Figure 8, element 820, 830
means for writing a deterministic pattern to a memory data word specified by the current memory address using the plurality of shared BIST resources;
Figure 8, element 841
means for incrementing the current memory address to a subsequent memory address using the plurality of shared BIST resources; and
Figure 3, element 321
means for determining if the current memory address equals a maximum memory address.
Figure 3, element 313
Claim 8
means for executing a built-in self-test (BIST) process on a plurality of processors and a plurality of memories in the computing system during built-in self-test (BIST) mode; and
Figure 8, element 820, 830
means for enabling the BIST mode in the computing system.
Figure 3, element 310
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 6 – 9, and 14 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., U.S. Publication 2012/0072789 (herein Chen).
Regarding claim 1, Chen discloses: An apparatus comprising: a memory configured to store a memory data word (figure 1, element F1); and a memory built-in self-test (MBIST) module coupled to the memory, the MBIST module configured to implement diagnostic check of the memory and to initialize the memory with a deterministic pattern (figure 1 element BIST Slave 1; paragraph 0024, 0027) and a pattern size congruent to a size of the memory data word (paragraph 0016, 0035, 0042).
Regarding claim 2, Chen discloses: a processor coupled to the memory (figure 1, element 12); and a logical built-in self-test (LBIST) module coupled to the processor, the LBIST module configured to validate logic functionality of the processor (paragraph 0037).
Regarding claim 3, Chen discloses: the MBIST module is further configured to write the deterministic pattern to the memory data word specified by a current memory address using a plurality of shared built-in self-test (BIST) resources (paragraph 0006).
Regarding claim 6, Chen discloses: the MBIST module is further configured to increment the current memory address to a subsequent memory address using the plurality of shared BIST resources (paragraph 0003, 0026).
Regarding claim 7, Chen discloses: An apparatus for implementing deterministic memory initialization, the apparatus comprising: means for initializing a current memory address in a plurality of memories to a memory address using a plurality of shared built-in self-test (BIST) resources in a computing system (figure 1, element BIST slave 1; paragraph 0024, 0027); means for writing a deterministic pattern to a memory data word specified by the current memory address using the plurality of shared BIST resources (paragraph 0006), wherein the deterministic pattern has a pattern size congruent to a size of the memory data word (paragraph 0016, 0035, 0042); means for incrementing the current memory address to a subsequent memory address using the plurality of shared BIST resources (figure 1, element BIST slave 1; paragraph 0006, 0026); and means for determining if the current memory address equals a maximum memory address (paragraph 0026).
Regarding claim 8, Chen discloses: means for executing a built-in self-test (BIST) process on a plurality of processors and a plurality of memories in the computing system during built-in self-test (BIST) mode (figure 1, element 12); and means for enabling the BIST mode in the computing system (figure 3, element 30).
Regarding claim 9, Chen discloses: A method comprising: initializing a first current memory address in a plurality of memories to a first memory address using a plurality of shared built-in self-test (BIST) resources (figure 1, element BIST slave 1; paragraph 0024, 0027); writing a first deterministic pattern to a first memory data word specified by the first current memory address using the plurality of shared BIST resources (paragraph 0006), wherein the deterministic pattern has a pattern size congruent to a size of the memory data word (paragraph 0016, 0035, 0042); and incrementing the first current memory address to a first subsequent memory address using the plurality of shared BIST resources (figure 1, element BIST slave 1; paragraph 0006, 0026).
Regarding claim 14, Chen discloses: determining if the first current memory address equals a maximum memory address (paragraph 0026).
Regarding claim 15, Chen discloses: writing a second deterministic pattern to a second memory data word specified by the first subsequent memory address using the plurality of shared BIST resources (figure 1, element BIST slave 1; paragraph 0006, 0024, 0027); incrementing the first subsequent memory address to a second subsequent address using the plurality of shared BIST resources (figure 1, element BIST slave 1; paragraph 0006, 0026); and determining if the second subsequent memory address equals the maximum memory address (paragraph 0026).
Regarding claim 16, Chen discloses: executing a built-in self-test (BIST) process on a plurality of processors and a plurality of memories in a computing system during built-in self-test (BIST) mode (figure 1, element 12).
Regarding claim 17, Chen discloses: selecting the first deterministic pattern to initialize the first memory data word to a known value (paragraph 0006).
Regarding claim 18, Chen discloses: the first subsequent memory address is equal to the first current memory address plus a programmable positive offset value (figure 1, element BIST slave 1; paragraph 0006, 0026).
Regarding claim 19, Chen discloses: the first subsequent memory address is equal to the first current memory address minus a programmable negative offset value (figure 1, element BIST slave 1; paragraph 0006, 0026).
Regarding claim 20, Chen discloses: enabling the BIST mode in the computing system, wherein the first current memory address is initialized in the plurality of memories to the first memory address using the plurality of shared BIST resources in the computing system (figure 3, element 30).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5 10, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Treuer, U.S. Patent 6,694,461 (herein Treuer).
Regarding claim 4, Chen teaches the limitations of the parent claim. Chen does not explicitly teach: the deterministic pattern is a pseudorandom sequence generated by a finite state machine.
Treuer teaches: the deterministic pattern is a pseudorandom sequence generated by a finite state machine (abstract).
One of ordinary skill in the art, at the time of the effective filing date of the invention, would find it obvious to combine the teaching of Chen: a memory built-in self-test (MBIST) module coupled to the memory, the MBIST module configured to implement diagnostic check of the memory and to initialize the memory with a deterministic pattern; with the teaching of Treuer: allowing for primitive polynomial-based pseudo-random bit-streams to be shifted into the address generator… utilize the address values to generate data values to be stored in a memory under test, for the purpose of generating data values (abstract). MBIST is well-known in the art (abstract). Pseudo-random is a well-known design choice in the art (abstract). One of ordinary skill in the art would recognize the use of well-known design choice would yield a predictable result.
Regarding claim 5, Chen teaches the limitations of the parent claim. Chen does not explicitly teach: the memory data word includes an associated parity word.
Treuer teaches: the memory data word includes an associated parity word (column 8, lines 5 – 15).
One of ordinary skill in the art, at the time of the effective filing date of the invention, would find it obvious to combine the teaching of Chen: a memory built-in self-test (MBIST) module coupled to the memory, the MBIST module configured to implement diagnostic check of the memory and to initialize the memory with a deterministic pattern; with the teaching of Treuer: a single-bit-per-word storage cell array, we calculate the parity of 2 LSB (column 8, lines 5 – 15). Data for storage is well-known in the art (abstract). Parity is a well-known design choice in the art (abstract). One of ordinary skill in the art would recognize the use of well-known design choice would yield a predictable result. And in view of the motivation previously stated above, for claim 4, the claim is rejected.
Regarding claim 10, Chen teaches the limitations of the parent claim. Chen does not explicitly teach: the first deterministic pattern is all zeros.
Treuer teaches: the first deterministic pattern is all zeros (column 13, lines 35 – 40). And in view of the motivation previously stated above, for claim 4, the claim is rejected.
Regarding claim 11, Chen teaches the limitations of the parent claim. Chen does not explicitly teach: the deterministic pattern is a pseudorandom sequence generated by a finite state machine.
Treuer teaches: the deterministic pattern is a pseudorandom sequence generated by a finite state machine (abstract). And in view of the motivation previously stated above, for claim 4, the claim is rejected.
Regarding claim 13, Chen teaches the limitations of the parent claim. Chen does not explicitly teach: the first memory data word includes an associated parity word.
Treuer teaches: the memory data word includes an associated parity word (column 8, lines 5 – 15). And in view of the motivation previously stated above, for claim 5, the claim is rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang, Laung-Terng et al. US 20020138801 A1
GLOEKLER; TILMAN et al. US 20150113346 A1
SHIBAHARA; Shinichi et al. US 20160349322 A1
Chung; Shine Chien US 20070136626 A1
Ansari; Ahmad R. US 20170168841 A1
Tonoyan; Smbat et al. US 20230409452 A1
Dorsey, Michael C. US 20030074621 A1
FELIX; Stephen et al. US 20230114044 A1
KANDULA; Rakesh et al. US 20240329130 A1
EASWARAN; et al. US 20250277853 A1
Ziaja; Thomas Alan et al. US 11428737 B1
a memory built-in self-test (MBIST) module coupled to the memory, the MBIST module configured to implement diagnostic check of the memory and to initialize the memory with a deterministic pattern.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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