Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/04/2026 has been entered.
Claims 12 is cancelled.
Claims 1, 7, and 9 are amended.
Claims 1 – 11 and 13 – 20 are pending.
Response to Arguments
Applicant's arguments filed 08/04/20206 have been fully considered but they are not persuasive.
Applicant argues “Chen does not disclose the element of "initialize the memory with a deterministic pattern using a sequencer and a MBIST server" or the element of "writing a deterministic pattern to a memory data word specified by the current memory address using the plurality of shared BIST resources, a sequencer and a memory built-in self-test MBIST server" as recited in amended pending claims.”
Specifically applicant argues: there is no disclosure in Chen of a "sequencer" nor a "MBIST server" as recited in the pending claims of the present application, as amended.
The Examiner disagrees.
The Examiner asserts that “sequencer” and “MBIST server” as disclosed in the specification are disclosed by Chen.
Applicant discloses a “sequencer” in paragraphs 0032, 0041, as disclosed by applicant, “a sequencer may be used to enter MBIST mode”.
Paragraph 0041 specifically discloses: “In one example, an application processor subsystem (APSS) sequencer 810 connects to a memory built-in self-test (MBIST) server 820 over an APSS software interface 811 to initialize a memory built-in self-test (MBIST) controller in MBIST mode”. However, the examiner notes under a broadest reasonable interpretation of the claims the claim language “sequencer” is not limited to a single example of a “application processor subsystem (APSS) sequencer”.
Chen discloses “a sequencer may be used to enter MBIST mode”, paragraph 0008. Chen specifically discloses “the master MBST circuitry is configured to issue a global built-in self initialization(BISI) instruction directing the multiple MBIST slave circuits to input initialization vectors in parallel into their respective associated arrays in order to quickly set the memory components of the arrays into a desired state for integrated circuit operation”. The examiner asserts one of ordinary skill in the art, at the time of filing, would understand a “self initialization(BISI) instruction directing the multiple MBIST slave circuits” to be a mechanism for initialization and result in entering BIST mode.
Applicant discloses a “MBIST server” in paragraph 0030, 0033, and 0041, as cited by applicant.
Paragraph 0030 discloses “In one example, the MBIST server 430 includes a first MBIST sub-server 431 with a first plurality of MBIST processors 433 and a second MBIST sub-server 432 with a second plurality of MBIST processors 434 as well as a third plurality of MBIST processors 435”. However, the examiner notes under a broadest reasonable interpretation of the claims the broad claim language “MBIST server” is not limited to a single example.
Additionally, Chen figure 1 discloses a hierarchy of MBIST controllers as disclosed in paragraph 0030.
Paragraph 0033 discloses “enter MBIST mode by enabling a BIST mode (e.g., setting Bist_iso_en to 1). In line 620, enable MBIST server (e.g., called from an application processor subsystem APSS)”. The examiner asserts enabling a MBIST mode in a MBIST server would be well understood in the art.
Paragraph 0041 discloses “In one example, the MBIST server 820 connects to a memory built-in self-test (MBIST) subserver 830 over a serial interface 821 to transport a plurality of serial signals”. Chen discloses in figure 1, element 12 and F1 disclose a hierarchical MBIST structure, as disclosed, with sub-servers in communication with memory (figure 1, element F1). Chen is silent regarding “serial signals”, however, the examiner notes under a broadest reasonable interpretation of the claims the broad claim language “MBIST server” is not limited to a single example.
In light of the arguments above the rejection of the amended claims is maintained in light of Chen.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 3, 6 – 9, and 14 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., U.S. Publication 2012/0072789 (herein Chen).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5 10, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, in view of Treuer, U.S. Patent 6,694,461 (herein Treuer).
Regarding claim 4, Chen teaches the limitations of the parent claim. Chen does not explicitly teach: the deterministic pattern is a pseudorandom sequence generated by a finite state machine.
Treuer teaches: the deterministic pattern is a pseudorandom sequence generated by a finite state machine (abstract).
One of ordinary skill in the art, at the time of the effective filing date of the invention, would find it obvious to combine the teaching of Chen: a memory built-in self-test (MBIST) module coupled to the memory, the MBIST module configured to implement diagnostic check of the memory and to initialize the memory with a deterministic pattern; with the teaching of Treuer: allowing for primitive polynomial-based pseudo-random bit-streams to be shifted into the address generator and utilize the address values to generate data values to be stored in a memory under test, for the purpose of generating data values (abstract). MBIST is well-known in the art (abstract). Pseudo-random is a well-known design choice in the art (abstract). One of ordinary skill in the art would recognize the use of well-known design choice would yield a predictable result.
Regarding claim 5, Chen teaches the limitations of the parent claim. Chen does not explicitly teach: the memory data word includes an associated parity word.
Treuer teaches: the memory data word includes an associated parity word
(column 8, lines 5 - 15).
One of ordinary skill in the art, at the time of the effective filing date of the invention, would find it obvious to combine the teaching of Chen: a memory built-in self-test (MBIST) module coupled to the memory, the MBIST module configured to implement diagnostic check of the memory and to initialize the memory with a deterministic pattern; with the teaching of Treuer: a single-bit-per-word storage cell array, we calculate the parity of 2 LSB (column 8, lines 5 - 15). Data for storage is well-known in the art (abstract). Parity is a well-known design choice in the art (abstract). One of ordinary skill in the art would recognize the use of well-known design choice would yield a predictable result. And in view of the motivation previously stated above, for claim 4, the claim is rejected.
Regarding claim 10, Chen teaches the limitations of the parent claim. Chen does not explicitly teach: the first deterministic pattern is all zeros.
Treuer teaches: the first deterministic pattern is all zeros (column 13, lines 35 - 40). And in view of the motivation previously stated above, for claim 4, the claim is rejected.
Regarding claim 11, Chen teaches the limitations of the parent claim. Chen does not explicitly teach: the deterministic pattern is a pseudorandom sequence generated by a finite state machine.
Treuer teaches: the deterministic pattern is a pseudorandom sequence generated by a finite state machine (abstract). And in view of the motivation previously stated above, for claim 4, the claim is rejected.
Regarding claim 13, Chen teaches the limitations of the parent claim. Chen does not explicitly teach: the first memory data word includes an associated parity word.
Treuer teaches: the memory data word includes an associated parity word (column 8, lines 5 - 15). And in view of the motivation previously stated above, for claim 5, the claim is rejected.
Closest Prior Arts of Record
Ziaja et al., U.S. Patent 11,428,737 (herein Ziaja)
Ziaja teaches: an IC includes an array of processor units, arranged in two or more subarrays. A subarray has a test generator, a multiplexer to apply a test vector to a datapath, and a test result output. It includes one or more processor units. A test result compressor is coupled with an output of the datapath, and compresses output data to obtain a test signature, which it stores in a signature register. The signature register is legible from outside the subarray. The datapath includes one or more memories and one or more ALUs. Test data travels through the full datapath, including the memories and the ALUs. ALU control registers are overridden during test to ensure a testable datapath.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang, Laung-Terng et al. US 20020138801 A1
GLOEKLER; TILMAN et al. US 20150113346 A1
SHIBAHARA; Shinichi et al. US 20160349322 A1
Chung; Shine Chien US 20070136626 A1
Ansari; Ahmad R. US 20170168841 A1
Tonoyan; Smbat et al. US 20230409452 A1
Dorsey, Michael C. US 20030074621 A1
FELIX; Stephen et al. US 20230114044 A1
KANDULA; Rakesh et al. US 20240329130 A1
EASWARAN; et al. US 20250277853 A1
Ziaja; Thomas Alan et al. US 11428737 B1
a memory built-in self-test (MBIST) module coupled to the memory, the MBIST module configured to implement diagnostic check of the memory and to initialize the memory with a deterministic pattern.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL F MCMAHON whose telephone number is (571)270-3232. The examiner can normally be reached Monday-Thursday 9am - 5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Daniel F. McMahon/Primary Examiner, Art Unit 2111
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