Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated July 25, 2024, claims 1-20 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed July 25, 2024 have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 1 and 20, lines 3 and 4, the phrase “between the plurality of bit lines and on lower portions of the plurality of bit lines” is unclear. Figure 11 of the disclosure shows shielding bit line [SBL] is between the bit lines [BLs], however, it is unclear how the structure is related to the lower portions of the bit lines. What are the lower portions of the bit lines?
Similarly, claim 12 recites the phrases “on lower portions of the first bit lines” and ““on lower portions of the second bit lines”. It is unclear what the lower portions of the bit lines are.
The dependent claims, claims 2-11 and 12-19, are rejected because they depend on the indefiniteness of the claims from which they depend.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Kajigaya [US Patent Application # 20120113736].
With respect to claim 1, Kajigaya discloses a memory device [figs. 1-3, 6 and 7] comprising: a memory cell array [fig. 3] including a plurality of bit lines [even GBL’s] to which a plurality of memory cells are connected [via LSA’s], and a shielding bit line [“…each of the odd-numbered global bit lines GBL(LO) and GBL(RO) is maintained at the precharge voltage VGBP, and thus functions as a shield between the adjacent even-numbered global bit lines GBL. “ – par. 0055] arranged between the plurality of bit lines and on lower portions of the plurality of bit lines; a sense amplifier [GSA’s] connected between a first sensing driving signal line [coupled to S11] and a second sensing driving signal line [coupled to S21], and configured to sense and amplify data stored in a memory cell selected from among the plurality of memory cells; a voltage generation circuit [via 17 and 18] configured to generate a bit line precharge voltage [VGBP] and an internal power voltage [read voltage – par. 0050] based on a power voltage of the memory device [although not explicitly depicted, the device’s internal voltage generation circuitry requires an underlying main power input [Vcc/Vdd] to produce the specified reference levels for memory operation]; and a control circuit [12] configured to selectively provide the shielding bit line with the bit line precharge voltage or the internal power voltage, wherein a level of the internal power voltage is greater than a level of the bit line precharge voltage [“additionally a precharge voltage is supplied to non-selected global bit lines until just before the amplifying by the sense amplifiers for the purpose of suppressing noise between adjacent bit lines in a read operation…” – par. 0007. It is noted that the purpose of this technique in hierarchical bit line structures is to maintain non-selected bit lines at a higher potential (often Vdd or a precharge level) to act as a shield against capacitive coupling from adjacent, active bit lines that are discharging during a read operation, thereby reducing noise).
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 January 9, 2026