DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. A more accurate and descriptive title might be, “Semiconductor device with heat dissipation for high-power processors”.
The disclosure is objected to because of the following informalities: [0034], [00109] and [00110] reference numeral “910A” should read “910”. Appropriate correction is required.
Claim Objections
Claim 17 objected to because of the following informalities: The claim uses the terms “HTC” and “LCTE” without providing definitions.. Appropriate correction is required. Please provide definitions of acronyms before their use.
Claim 17 is objected to because of the following informalities: "semiconductor device according claim 1" is missing the preposition "to". It should read, “according to claim 1”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 12 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cho et al (US 2023/0207414 Al, hereinafter Cho).
Regarding Claim 1, Cho discloses, in Figure 8A, a semiconductor device, comprising:
a substrate, item 210 [0071];
a memory component, item 221 (which includes elements 11 and 12, [0039], shown in Figure 8A as well as Figure 1) disposed on the substrate;
and a heat dissipation component (elements 251 and 252, Figure 8A, element [0071]) disposed on the substrate;
wherein the heat dissipation component has a thermal conductivity greater than that of silicon (Abstract, Summary, [0005], [0056], [0057]).
Regarding Claim 2, Cho discloses, [0056], a semiconductor device according to claim 1, wherein the heat dissipation component is made of a material comprising diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, metal (copper) or a combination thereof.
Regarding Claim 3, Cho discloses, [0071], a semiconductor device according claim 1, wherein the memory component and the heat dissipation component are disposed side by side (Figure 8A, Items 221 and 252).
Regarding Claim 4, Cho discloses a semiconductor device according claim 1, further comprising:
a plurality of heat dissipation components (Figure 8A, items 251 and 252);
wherein the memory component (item 221) is disposed between the heat dissipation components.
Regarding Claim 5, Claim 1 is reinterpreted as follows:
Cho discloses, in Figure 17A, a semiconductor device, comprising:
a substrate, item 103 [0081];
a memory component, a combination of items 121 and 122 (which includes elements 11 and 12, [0039]) disposed on the substrate;
and a heat dissipation component (element 151, Figure 17A, [0030]) disposed on the substrate;
wherein the heat dissipation component has a thermal conductivity greater than that of silicon (Abstract, Summary, [0005], [0056], [0057]).
Specifically, to Claim 5, Cho discloses a semiconductor device according claim 1, further comprising:
a plurality of the memory components (Figure, 17A, memory components, 121, appear on left side and right side of structure);
wherein the heat dissipation component (item 151) is disposed between the memory components.
Regarding Claim 6, Claim 1 is reinterpreted as follows:
Cho discloses, in Figure 8A, a semiconductor device, comprising:
a substrate, item 210 [0071];
a memory component, a combination of items 221 and 222 (which includes elements 11 and 12, [0039]) disposed on the substrate;
and a heat dissipation component (element 252, Figure 8A) disposed on the substrate;
wherein the heat dissipation component has a thermal conductivity greater than that of silicon (Abstract, Summary, [0005], [0056], [0057]).
Specifically, regarding Claim 6, Cho discloses a semiconductor device according claim 1, further comprising:
a molding compound (element 251, Figure 8A) disposed between the memory component and the heat dissipation component.
Regarding Claim 7, Claim 1 is reinterpreted as follows:
Cho discloses, in Figure 8A, a semiconductor device, comprising:
a substrate, item 210 [0071];
a memory component, a combination of items 221 and 222 (which includes elements 11 and 12, [0039]) disposed on the substrate;
and a heat dissipation component (element 252, Figure 8A) disposed on the substrate;
wherein the heat dissipation component has a thermal conductivity greater than that of silicon (Abstract, Summary, [0005], [0056], [0057]).
Specifically, regarding Claim 7, Cho discloses a semiconductor device according claim 1, further comprising:
a plurality of the heat dissipation components (252 on the left, and 252 on the right, Figure 8A); and
a molding compound (251) disposed between the heat dissipation components.
Regarding Claim 8, Claim 1 is reinterpreted as follows:
Cho discloses, in Figure 17A, a semiconductor device, comprising:
a substrate, item 103 [0081];
a memory component, a combination of items 121 and 122 (which includes elements 11 and 12, [0039]) disposed on the substrate;
and a heat dissipation component (element 151 on the lefthand side of Figure 17A, [0030]) disposed on the substrate;
wherein the heat dissipation component has a thermal conductivity greater than that of silicon (Abstract, Summary, [0005], [0056], [0057]).
Specifically, regarding Claim 8, Cho discloses (Figure 17A) the semiconductor device according claim 1, further comprising:
a plurality of the memory components (121/122 on the lefthand and righthand side); and
a molding compound (element 151, located between the memory components, 121/122 on left and right sides) disposed between the memory components.
Regarding Claim 12, Cho discloses the semiconductor device according claim 1, wherein the substrate comprises:
a back-end-of-line (BEOL) structure (Figure 8A, element 240); and
a thermal Isolation structure (element 241) disposed on and/or within the BEOL structure. Cho, Figure 8A, shows that element 241 is a thermal isolation structure, which corresponds to element 141, Figure 1A, see [0071]. Furthermore, [0054] discloses that 141 may include glass or ceramic.
Regarding Claim 13, Claim 1 is reinterpreted as follows:
Cho discloses, in Figure 8A, a semiconductor device, comprising:
a substrate, item 210 [0071];
a memory component, a combination of items 221 and 222 (which includes elements 11 and 12, [0039]) disposed on the substrate;
and a heat dissipation component (element 252, Figure 8A) disposed on the substrate;
wherein the heat dissipation component has a thermal conductivity greater than that of silicon (Abstract, Summary, [0005], [0056], [0057]).
Specifically, regarding Claim 13, Cho discloses the semiconductor device according claim 1, wherein the substrate comprises:
a BEOL structure (element 240); and
a heat spreading structure (Figure 8A, element 251) disposed on and/or within the BEOL structure.
Therefore, Cho anticipates Claims 1-8, 12 and 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Edmunds US 2010/0128436 Al (hereinafter Edmunds).
Cho discloses the semiconductor device according to claim 1. Cho does not disclose the elements of Claim 9.
Edmunds teaches (Figure 5) a heat spreader (18, [0021]) comprising a vapor chamber (24, [0021]), covering a memory component and a heat dissipation component and having an upper surface; a cooling component [Figure 2; [0020], 16) disposed on [a lower side of] the upper surface of the heat spreader and having a fluid channel (Figure 2; [0020], fluid channels, 30); and [0021] teaches an internal fluid cooling component, which inherently must have a fluid channel a fan (Figure 5; 49, [0027]) and/or a heat exchanger thermally coupled to the cooling component. Therefore, it would be obvious to a POSITA to combine the teachings of Edmunds with the semiconductor device of Cho in order to provide heat dissipation and cooling.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Edmunds. Cho discloses the semiconductor device according to claim 9, further comprising:
Regarding Claim 10, Cho discloses the semiconductor device according to claim 9, further comprising:
a molding compound (Figure 8A; item 230) on a lateral surface of the heat dissipation component (item 252) and having a lateral surface;
wherein the lateral surface of the molding compound and a lateral surface of the substrate (item 21) are flushed with each other (as shown in Figure 8A).
Therefore, it would be obvious to a POSITA to combine the teachings of Edmunds with the semiconductor device of Cho in order to provide heat dissipation and cooling.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Umezawa 1999 US 5,990,550 (hereinafter Umezawa).
Cho discloses the semiconductor device according to claim 1, wherein the substrate (210; Figure 8A) comprises:
a power rail layer, item 212, Figure 8A, [0031] and [0071]. (212 is connected to the through-silicon via 235, providing power to the device, thus functioning as a power rail layer.)
a power supply layer (Figure 8A; item 208) connected with the power rail layer, (208 is connected to the power rail 212 to provide electrical power to the device).
Cho does not disclose an interposer disposed adjacent to and thermally coupled to the power supply layer, wherein the interposer is made of diamond, aluminum nitride, boron nitride, boron arsenide, silicon carbide, metal or a combination thereof.
Umezawa teaches an integrated circuit mounted on an interposer substrate (item 3, Figure 2; column 3, 11-16) made of aluminum nitride. It is well known in the art that aluminum nitride is both a high-thermal-conductivity (HTC) and low coefficient of thermal expansion (LCTE) material. When Cho’s device is combined with Umezawa’s interposer, the interposer (item 3) is disposed adjacent to and thermally coupled to the power supply layer (212).
Therefore, it would be obvious to a POSITA to combine the semiconductor device of Cho with the aluminum nitride substrate taught by Umezawa in order to improve heat dissipation.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Park, US 2016/0210234 Al (hereinafter Park) and Cook et al, US 2018/0151464 Al (hereinafter Cook).
Regarding Claim 14, Cho does not disclose a processor core, cache memory, a thermal metamaterial structure, as currently claimed.
Park teaches:
a processor core; (Figure 2, item 100);
a cache memory (Figure 2, item 110) disposed adjacent to the processor core; wherein a main memory (Figure 2, item 200) similar to Cho’s memory component is incorporated with the processor core and cache memory.
Cook teaches a thermal metamaterial structure (Figure 5B, items 530, 532, and 534; [0052] that surrounds the heat generating components to divert heat.
It would have been obvious to a POSITA to combine the semiconductor device of Cho with the processor core and cache memory as taught by Park in order to provide functional computing device. Furthermore, it would have been obvious to a POSITA to combine the resulting combination with the thermal metamaterial structure as taught by Cook in order to remove heat from thermally sensitive components. This thermal metamaterial would be placed between the processor core and the cache memory, and between the cache memory and the memory component in order to reduce thermal cross-talk.
Regarding Claims 15 and 16, Cook discloses the thermal metamaterial structure that is a thermal-guiding ring (Figure 5B, items 504, 532 and 535) comprising:
a first layer (504) having a first thermal conductivity (silicon, [0018]; note that 104 corresponds to item 504, Figure 5B);
a second (535) layer having a second thermal conductivity and surrounding the first layer (graphene, [0023]; note that 135 corresponds to item 535, Figure 5B); and
a third layer (532) having a third thermal conductivity and surrounding the second layer (silicon dioxide, [0020]; note that 132 corresponds to item 532, Figure 5B);
wherein the second thermal conductivity is greater than the first thermal conductivity, and the first thermal conductivity is greater than the third thermal conductivity.
Therefore, Cho in view of Park and Cook renders Claims 15 and 16 to be obvious.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Umezawa.
Cho discloses the semiconductor device according to claim 1. Cho does not disclose where the semiconductor device is mounted on a HTC and LCTE substrate.
Umezawa teaches an integrated circuit mounted on an interposer substrate (item 3, Figure 2; column 3, 11-16) made of aluminum nitride. It is well known in the art that aluminum nitride is both a high-thermal-conductivity (HTC) and low coefficient of thermal expansion (LCTE) material. Therefore, it would be obvious to a POSITA to combine the semiconductor device of Cho with the aluminum nitride substrate taught by Umezawa in order to improve heat dissipation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL MORRIS WASSERBURG whose telephone number is (571)272-0518. The examiner can normally be reached Mon - Friday 8AM - 5PM.
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/DANIEL M WASSERBURG/ Examiner, Art Unit 2892
/NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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