Prosecution Insights
Prosecution Insights
Technology area: Semiconductors, Circuits & Optics
8 pending office actions • 6 art units • 8 examiners • 0 of 8 (0%) have an AI response strategy ready • 22 patents granted in the last 365 days
Etron Technology Inc. currently has 8 pending office actions in the Semiconductors, Circuits & Optics technology area. These 8 actions are handled by 8 distinct examiners. These matters are distributed across 6 distinct art units.
The busiest examiner for the portfolio is ZARNEKE, DAVID A, who is responsible for 1 pending office action. With 8 pending office actions and 8 distinct examiners, the workload is distributed with no examiner overlap. The 6 distinct art units involved indicate that the company's semiconductor and optical innovations are being reviewed in 6 different specialized sections of the patent office. This requires the company to manage 8 different examiners across 6 art units, which may lead to varied prosecution experiences despite the shared technology area.
Based on the USPTO statutory response window for each pending office action. 4 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 4 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §101 + other | 1 (12%) |
| §103 only | 3 (38%) |
| Multi-statute (no §101) | 4 (50%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| ZARNEKE, DAVID A | 1 | 71.0% | +11.2% |
| WASSERBURG, DANIEL MORRIS | 1 | — | — |
| NGUYEN, DUY T V | 1 | 78.9% | +16.7% |
| LEE, CHUN KUAN | 1 | 68.4% | +3.7% |
| KIELIN, ERIK J | 1 | 67.6% | +5.1% |
| WALL, VINCENT | 1 | 62.5% | +24.4% |
| PROSTOR, ANDREW VICTOR | 1 | 95.1% | +6.9% |
| DOAN, TRANG T | 1 | 83.0% | +16.8% |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 5 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17969447 | DATA COLLECTION AND ANALYSIS SYSTEM AND DEVICE | DOAN, TRANG T | 5d overdue |
| 18542032 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME | WALL, VINCENT | 75d |
| 18785296 | SEMICONDUCTOR DEVICE | WASSERBURG, DANIEL MORRIS | — |
| 18634481 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME | NGUYEN, DUY T V | — |
| 18471670 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE SIDE INTERCONNECTION AND METHOD OF FORMING THE SAME | PROSTOR, ANDREW VICTOR | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 4 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17969447 | DATA COLLECTION AND ANALYSIS SYSTEM AND DEVICE | DOAN, TRANG T | 5d overdue |
| 18542032 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME | WALL, VINCENT | 75d |
| 19214066 | COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE | ZARNEKE, DAVID A | 86d |
| 18634481 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME | NGUYEN, DUY T V | — |
| Art Unit | Apps |
|---|---|
| 2891 | 1 |
| 2181 | 1 |
| 2814 | 1 |
| 2898 | 1 |
| 2812 | 1 |
| 2431 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 19214066 | COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE | ZARNEKE, DAVID A | 2891 | §103 | Final Rejection | 86d | Pending | May 21, 2025 |
| 18785296 | SEMICONDUCTOR DEVICE | WASSERBURG, DANIEL MORRIS | — | §102§103 | Non-Final OA | — | Pending | Jul 26, 2024 |
| 18634481 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME | NGUYEN, DUY T V | — | §102§103 | Non-Final OA | — | Pending | Apr 12, 2024 |
| 18600820 | MEMORY SYSTEM AND MEMORY CHIP | LEE, CHUN KUAN | 2181 | §103 | Non-Final OA | 46d | Pending | Mar 11, 2024 |
| 18592521 | SEMICONDUCTOR PACKAGE FOR LIQUID IMMERSION COOLING AND METHOD OF FORMING THE SAME | KIELIN, ERIK J | 2814 | §103 | Non-Final OA | — | Pending | Mar 01, 2024 |
| 18542032 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME | WALL, VINCENT | 2898 | §102§103 | Final Rejection | 75d | Pending | Dec 15, 2023 |
| 18471670 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE SIDE INTERCONNECTION AND METHOD OF FORMING THE SAME | PROSTOR, ANDREW VICTOR | 2812 | §102§103§112 | Non-Final OA | — | Pending | Sep 21, 2023 |
| 17969447 | DATA COLLECTION AND ANALYSIS SYSTEM AND DEVICE | DOAN, TRANG T | 2431 | §101§103§112Other | Final Rejection | 5d overdue | Pending | Oct 19, 2022 |
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