Prosecution Insights
Last updated: August 14, 2026

Etron Technology Inc.

8 pending office actions • 6 art units • 8 examiners • 0 of 8 (0%) have an AI response strategy ready • 16 patents granted in the last 365 days

Portfolio Summary

8
Total Pending OAs
5
Non-Final OAs
3
Final Rejections
0
Advisory / Quayle

Response Deadline Pressure

Based on the USPTO statutory response window for each pending office action. 4 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.

1
Overdue
1
Due this week
0
Due this month
0
Due in next 60 days
2
Due later

Deadline Fire Line

Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 4 of the docket's apps have a known mailing date.

-30dToday30d60d90d120d
Overdue (1)Due ≤ 7 days (1)Due later (2)

Case Difficulty Mix

Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.

5
Hard (62%)
3
Medium (38%)
0
Easy (0%)
0
Unknown (0%)

Rejection Statute Mix

BucketCases
§101 + other1 (12%)
§103 only3 (38%)
Multi-statute (no §101)4 (50%)

Industry Mix

How the docket's pending cases split across USPTO tech-center bands.

0
Life Sciences
0% of docket
2
Information Tech
25% of docket
0
Communications
0% of docket
6
Semiconductors
75% of docket
0
Mechanical / Eng
0% of docket
0
Business / Other
0% of docket

Time-on-OA Estimate

Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.

80 h
Manual time on pending OAs
16 h
Time saved (low, 20%)
28 h
Time saved (mid, 35%)
0.7 wks
FTE-weeks freed (mid)

Top Examiners on this docket

ExaminerApps on this docketAllow rateInterview lift
ZARNEKE, DAVID A 1 70.8% +10.8%
LEE, CHUN KUAN 1 68.3% +3.8%
WALL, VINCENT 1 62.2% +24.3%
HUTSON, NICHOLAS LELAND 1 60.0% +16.7%
PROSTOR, ANDREW VICTOR 1 97.2% +4.0%
ERDEM, FAZLI 1 85.3% +16.0%
DOAN, TRANG T 1 82.9% +16.9%
ZABEL, ANDREW JOHN 1 85.3% +21.7%

Quick Wins (1)

Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 1 ordered by deadline are shown.

App #TitleExaminerDue in
18231547 MANUFACTURING METHOD OF DIAMOND COMPOSITE WAFER ERDEM, FAZLI 7d

Hard Cases (5)

Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 5 ordered by deadline are shown.

App #TitleExaminerDue in
17969447 DATA COLLECTION AND ANALYSIS SYSTEM AND DEVICE DOAN, TRANG T 5d overdue
18542032 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME WALL, VINCENT 75d
18473999 SEMICONDUCTOR PACKAGE STRUCTURE FOR ENHANCED COOLING HUTSON, NICHOLAS LELAND
18471670 SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE SIDE INTERCONNECTION AND METHOD OF FORMING THE SAME PROSTOR, ANDREW VICTOR
17854489 COMPOSITE SEMICONDUCTOR WAFER/CHIP FOR ADVANCED ICS AND ADVANCED IC PACKAGES AND THE MANUFACTURE METHOD THEREOF ZABEL, ANDREW JOHN

Interview Candidates (6)

Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 6 ordered by deadline are shown.

App #TitleExaminerDue in
17969447 DATA COLLECTION AND ANALYSIS SYSTEM AND DEVICE DOAN, TRANG T 5d overdue
18231547 MANUFACTURING METHOD OF DIAMOND COMPOSITE WAFER ERDEM, FAZLI 7d
18542032 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME WALL, VINCENT 75d
19214066 COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE ZARNEKE, DAVID A 86d
18473999 SEMICONDUCTOR PACKAGE STRUCTURE FOR ENHANCED COOLING HUTSON, NICHOLAS LELAND
17854489 COMPOSITE SEMICONDUCTOR WAFER/CHIP FOR ADVANCED ICS AND ADVANCED IC PACKAGES AND THE MANUFACTURE METHOD THEREOF ZABEL, ANDREW JOHN

Top Art Units

Art UnitApps
2818 2
2812 2
2891 1
2181 1
2898 1
2431 1

Pending Office Actions

App #TitleExaminerArt UnitStatutesStatusDue inAIFiled
19214066 COWOS IC STRUCTURE WITH EDGE-PAD SEMICONDUCTOR DIE ZARNEKE, DAVID A 2891 §103 Non-Final OA 86d Pending May 21, 2025
19008669 MEMORY CHIP AND MEMORY SYSTEM WITH THE SAME LEE, CHUN KUAN 2181 §103Other Non-Final OA Pending Jan 03, 2025
18542032 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME WALL, VINCENT 2898 §102§103 Non-Final OA 75d Pending Dec 15, 2023
18473999 SEMICONDUCTOR PACKAGE STRUCTURE FOR ENHANCED COOLING HUTSON, NICHOLAS LELAND 2818 §102§103 Final Rejection Pending Sep 25, 2023
18471670 SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE ASSEMBLY WITH EDGE SIDE INTERCONNECTION AND METHOD OF FORMING THE SAME PROSTOR, ANDREW VICTOR 2812 §102§103§112 Non-Final OA Pending Sep 21, 2023
18231547 MANUFACTURING METHOD OF DIAMOND COMPOSITE WAFER ERDEM, FAZLI 2812 §103 Non-Final OA 7d Pending Aug 08, 2023
17969447 DATA COLLECTION AND ANALYSIS SYSTEM AND DEVICE DOAN, TRANG T 2431 §101§103§112Other Final Rejection 5d overdue Pending Oct 19, 2022
17854489 COMPOSITE SEMICONDUCTOR WAFER/CHIP FOR ADVANCED ICS AND ADVANCED IC PACKAGES AND THE MANUFACTURE METHOD THEREOF ZABEL, ANDREW JOHN 2818 §102§103 Final Rejection Pending Jun 30, 2022

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