DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2 10-12, 13 17-18 and 19-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claims 1 and 13, they each recites, and a link area configured to electrically interconnect the base voltage line and the common electrode and disposed in the display area. It is unclear if the base voltage and common electrode are indeed interconnected. Configured to does not mean the action takes place. For example, A wallet configure to contain credit card, or cash does not mean the wallet comprise the cash or credit card only that it capable of containing cash and credit cards. In this instance it is unclear if the link area actually interconnect the base voltage and common electrode.
As to claims 1 13 and 19 assuming configured to means a link area between the plurality of light emitting elements and electrically interconnecting the first auxiliary electrode and the common electrode.
This is still unclear since it is unclear how an area per se electrically interconnects with anything. An area has no inherent electrical conductivity. It would have to be an element in the area. The broadest reasonable interpretation is the area contains no elements. Otherwise, applicant would have said a link area comprising an interconnection that interconnect the common electrode an the first auxiliary electrode. As such it is how just an area can perform the function claimed
Claims 3 and 14 sufficiently clarify the elements in the link area and the elements required to interconnect the common electrode and auxiliary electrode.
As to claims 2 and 12, recitation of wherein the element intermediate layer comprises a hole formed on the bank, and the link area electrically interconnects the base voltage line and the common electrode through the hole lack antecedent basis applicant has no establish the intermediate layer is on the bank only along the bank
As to claim 12, recitation of further comprising a plurality of subpixels, wherein the transistor is provided in plural, wherein each of the plurality of subpixels comprises a light emitting element and a transistor of the plurality of transistors, and wherein the light emitting element is configured by overlapping of the pixel electrode, the element intermediate layer, and the common electrode with each other, and the link area is located between a first subpixel and a second subpixel among the plurality of subpixels is unclear.
Specifically, what is meant by in plural and are the in plural the same of different than the transistor for each subpixel.
It is also unclear if each subpixel contains the pixel electrode or are they referring to the pixel electrode of claim 1.
As to claim 18, applicant does not link these elements to the existing structure and does not state how these elements interrelate to the elements already claimed.
As to claim 20, Applicant does not link the elements the to the elements of claim 19 specifically the link area: the link area comprises and a first portion of the common electrode on the first element intermediate layer, wherein the second light emitting element includes a second pixel electrode, a second element intermediate layer on the second pixel electrode and the bank, and a second portion of the common electrode on the second element intermediate layer, and a second auxiliary electrode coplanar with the first element intermediate layer and the second element intermediate layer, and interposed between the first element intermediate layer and the second element intermediate layer thus it is unclear if the link area is the same or different that the area already recited.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10, 11, 12 and 19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Baek 20210175460.
As to claims 1 and 19, Baek teaches A display device comprising: (see e.g. figure 2 3 5and 6j and 8) a substrate (item 100) comprising a display area and a non-display area adjacent the display area (this is arbitrary since applicant does not set forth any distinguishing structure but DP regions can be considered a non-display and other regions the display region); a transistor disposed over the substrate (item T); a base voltage line disposed over the substrate (item 114); a planarization layer disposed on the transistor and the base voltage line/auxiliary electrode (item 114 or 140); a pixel electrode disposed on the planarization layer (item 160); a bank disposed on the pixel electrode and comprising that does not cover a portion of the pixel electrode (exposes implies nothing is on the area or that it is exposed applicant later claims it is covered so the pixel electrode is not exposed Items 172-174 leaving a portion of item 160 uncovered) ; an element intermediate layer located on the pixel electrode through the opening of the bank in a light emitting area and extending along the bank in a non-light emitting area (see figure 3 item 180a specifically item 186); a common electrode disposed on the element intermediate layer (item 190 on 184 region); and a link area configured to electrically interconnect the base voltage line and the common electrode and disposed in the display area (item 162). Baek teaches a plurality of light emitting elements the bank between the plurality of light emitting elements (see e.g. 2-5 item 174 between each subpixel).
As to claim 10, Baek teaches wherein the common electrode is configured with a transparent electrode paragraph 152).
As to claim 11, Baek teaches wherein the link area comprises a material having a resistivity higher than that of the common electrode (the link area comprises bank insulators which has a higher resistivity than a conductor).
As to claim 12, Baek teaches the device comprises a plurality of subpixels wherein each subpixel comprises a transistor a pixel electrode and a light emitting element (figure 3-4 items T) and the element intermediate layer, and the common electrode with each other, and the link area is located between a first subpixel and a second subpixel among the plurality of subpixels (figure 5 item 172 between subpixel in a column direction)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 6-9,13-15, 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baek in view of Park 20230011322.
As to claims 2 and 13, Baek teaches A display device comprising: (see e.g. figure 2 3 5and 6j and 8) a substrate (item 100) comprising a display area and a non-display area adjacent the display area (this is arbitrary since applicant does not set forth any distinguishing structure but DP regions can be considered a non-display and other regions the display region); a transistor disposed over the substrate (item T); a base voltage line disposed over the substrate (item 114); a planarization layer disposed on the transistor and the base voltage line (item 140); a pixel electrode disposed on the planarization layer (item 160); a bank disposed on the pixel electrode and comprising that does not cover a portion of the pixel electrode (exposes implies nothing is on the area or that it is exposed applicant later claims it is covered so the pixel electrode is not exposed Items 172-174 leaver a portion of item 160 uncovered) ; an element intermediate layer located on the pixel electrode through the opening of the bank in a light emitting area and extending along the bank in a non-light emitting area (see figure 3 item 180a specifically item 186); a common electrode disposed on the element intermediate layer (item 190 on 184 region); and a link area configured to electrically interconnect the base voltage line and the common electrode and disposed in the display area (item 162).
Baek teaches a hole in the bank (item 172) It is unclear if Baek teaches wherein the element intermediate layer comprises a hole formed in the bank, and the link area electrically interconnects the base voltage line and the common electrode through the hole.
Park teaches wherein the element intermediate layer comprises a hole formed in the bank (region 20 figure 19 and 20 the holes in the 325), and the link area electrically interconnects the base voltage line and the common electrode through the hole (figures item 325 with holes, 340 connected through the holes to the base voltage).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to have formed the connection with holes through the intermediate layer in the bank region to use conventional techniques to provide interconnection between the common electrode and the voltage line.
As to claims 3 and 14, Baek teaches wherein the link area comprises: a first auxiliary electrode located under the planarization layer (item 140d); and a second auxiliary electrode located on the bank and electrically interconnecting the common electrode and the first auxiliary electrode (a portion of item 190 on the bank), wherein the second auxiliary electrode electrically interconnects the common electrode and the first auxiliary electrode through the hole (figure 19 of Park), and wherein the first auxiliary electrode is the base voltage line or an electrode electrically connected to the base voltage line (item 140d is connected or can be considered part of the voltage line).
As to claim 4 and 15, Baek and Park teach wherein the second auxiliary electrode is disposed inside the hole (the part of item 190 that is the auxiliary electrode is in the hole).
As to claim 6, Park teaches wherein the second auxiliary electrode contacts one or more side portions of the hole (figure 19 auxiliary electrode portion contacts sidewalls of the hole in item 325).
As to claim 7, Baek teaches wherein the link area further comprises a bridge electrode for electrical interconnecting the first auxiliary electrode and the second auxiliary electrode, and wherein the bridge electrode is located between the planarization layer and the bank (the horizontal portion of item 140d/162 can be considered a bridge and it is between the 140 and the bank).
As to claim 8, Baek teaches wherein the bridge electrode comprises a same material as the pixel electrode (items 160 and 162 are the same materials figure 9d).
As to claim 9, Baek teaches wherein the first auxiliary electrode comprises a same material as a source electrode or drain electrode of the transistor, or a same material as an electrode electrically connected to the source electrode or drain electrode of the transistor (item 140d/146 are form at the same time as the source and drain).
As to claim 17, Baek teaches wherein the link area is located in the display area (figure 2 and 5).
As to claim 18, Baek teaches data lines and gate lines but does not explicitly teach a data driving circuit to output data signals to a plurality of data lines of the display panel; a gate driving circuit to output gate signal to a plurality of gate lines of the display panel; and a display controller configure to control the data driving circuit and the gate driving circuit, and control driving timing for the plurality of data lines and driving timing for the plurality of gate lines.
However providing a data driving circuit to output data signals to a plurality of data lines of the display panel; a gate driving circuit to output gate signal to a plurality of gate lines of the display panel; and a display controller configure to control the data driving circuit and the gate driving circuit, and control driving timing for the plurality of data lines and driving timing for the plurality of gate lines was known at the time of filing to make the display functional.
Thus it would have been obvious to one of ordinary skill in the art at the time of filing to include for the display a data driving circuit to output data signals to a plurality of data lines of the display panel; a gate driving circuit to output gate signal to a plurality of gate lines of the display panel; and a display controller configure to control the data driving circuit and the gate driving circuit, and control driving timing for the plurality of data lines and driving timing for the plurality of gate lines to allow the display to function as a display.
Allowable Subject Matter
Claims 5 and 16 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Prior art fails to teach and or suggest, wherein the second auxiliary electrode is spaced apart from one or more side portions of the hole, the second auxiliary electrode does not contact the sidewalls of the whole.
Claim 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Prior art does not teach and or suggest the link area further comprises the plurality of light emitting elements include a first light emitting element and a second light emitting element, wherein the first light emitting element includes a first pixel electrode, a first element intermediate layer on the first pixel electrode and the bank, and a first portion of the common electrode on the first element intermediate layer, wherein the second light emitting element includes a second pixel electrode, a second element intermediate layer on the second pixel electrode and the bank, and a second portion of the common electrode on the second element intermediate layer, and a second auxiliary connected to the first auxiliary electrode and coplanar with the first element intermediate layer and the second element intermediate layer, and interposed between the first element intermediate layer and the second element intermediate layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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