DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/07/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Try to use Fig. 34A to reject all the claims. The remaining claims are tried for Fig. 33A. Then let it go.
Claim(s) 1 and 8-12 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ching et al. (US 2017/0207126 A1).
Regarding clam 1, Ching et al. teach in Fig. 33 (please also see Fig. 32B for structures under the ILD layer 1102 in Fig. 33) a semiconductor structure (200D, [0017]), comprising: a base fin (a lower portion of 3212 below half the height 3116; see Fig. 32B below, [0136, 0145]) protruding from a substrate (202; [0024]) and having a first sidewall surface (the left sidewall surface of a lower portion of 3212 below half the height 3116) opposing a second sidewall surface (the right sidewall surface of a lower portion of 3212 below half the height 3116); an isolation feature (402; [0032]) surrounding a lower portion of the base fin (a lower portion of a lower portion of 3212 below half the height 3116); a source/drain feature (an upper portion of 3212 above half the height 3116; [0145]) on the base fin (a lower portion of 3212 below half the height 3116) and having a third sidewall surface (the left sidewall surface of an upper portion of 3212 above half the height 3116) over the first sidewall surface (the left sidewall surface of a lower portion of 3212 below half the height 3116) and a fourth sidewall surface (the right sidewall surface of an upper portion of 3212 above half the height 3116) over the second sidewall surface (the right sidewall surface of a lower portion of 3212 below half the height 3116); a first spacer (the left 3110; [0136]) extending along the first sidewall surface (the left sidewall surface of a lower portion of 3212 below half the height 3116) and a lower portion of the third sidewall surface (a lower portion of the left sidewall surface of an upper portion of 3212 above half the height 3116; see Fig. 32B below) and having a first height (the height of the left 3110); a second spacer (the left half of 3108; [0136]) extending along the second sidewall surface (the right sidewall surface of a lower portion of 3212 below half the height 3116) and the fourth sidewall surface (the right sidewall surface of an upper portion of 3212 above half the height 3116) and having a second height (the height of the left half of 3108) greater than the first height (the height of the left 3110); and a dielectric layer (1102/3002 formed as a continuous dielectric layer, 3002 is a dielectric material located inside 3108 as shown in Fig. 31B; Fig. 33, [0068, 0128]) having a first portion (3002) spaced apart from the source/drain feature (an upper portion of 3212 above half the height 3116) by the second spacer (the left half of 3108) and a second portion (1102) over and in direct contact with top surfaces of the source/drain feature (an upper portion of 3212 above half the height 3116) and the second spacer (the left half of 3108; see Fig. 33).
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[AltContent: textbox (Source/drain feature: an upper portion of 3212 above half the height 3116)][AltContent: textbox (Base fin: an lower portion of 3212 below half the height 3116)]
Fig. 32B of Ching et al. (middle section)
Regarding clam 8, Ching et al. teach the semiconductor structure of claim 1, wherein the first spacer (the left 3110) is disposed adjacent to the source/drain feature (an upper portion of 3212 above half the height 3116) in a first direction (the horizontal direction in Fig. 33), and the third sidewall surface (the left sidewall surface of an upper portion of 3212 above half the height 3116) curves outwardly towards the first direction (the horizontal direction in Fig. 33).
Regarding clam 9, Ching et al. teach in Fig. 34B a semiconductor structure (200D, [0017]), comprising: a first source/drain feature (an upper portion of 3212 above half the height 3116; [0136, 0145]) over a substrate (202; [0024]) and having a first sidewall surface (the left sidewall surface of an upper portion of 3212 above half the height 3116) and a second sidewall surface (the right sidewall surface of an upper portion of 3212 above half the height 3116) opposing the first sidewall surface (the left sidewall surface of an upper portion of 3212 above half the height 3116); a second source/drain feature (an upper portion of 3214 above half the height 3116; [0136, 0145]) over the substrate (202) and adjacent the first source/drain feature (an upper portion of 3212 above half the height 3116), the second source/drain feature (an upper portion of 3214 above half the height 3116) having a third sidewall surface (the left sidewall surface of an upper portion of 3214 above half the height 3116) and a fourth sidewall surface (the right sidewall surface of an upper portion of 3214 above half the height 3116) opposing the third sidewall surface (the left sidewall surface of an upper portion of 3214 above half the height 3116), wherein the second sidewall surface (the right sidewall surface of an upper portion of 3212 above half the height 3116) is disposed between the first sidewall surface (the left sidewall surface of an upper portion of 3212 above half the height 3116) and the third sidewall surface (the left sidewall surface of an upper portion of 3214 above half the height 3116), and a distance between the first sidewall surface (the left sidewall surface of an upper portion of 3212 above half the height 3116) and the third sidewall surface (the left sidewall surface of an upper portion of 3214 above half the height 3116) is less than a distance between the first sidewall surface (the left sidewall surface of an upper portion of 3212 above half the height 3116) and the fourth sidewall surface (the right sidewall surface of an upper portion of 3214 above half the height 3116); an isolation feature (3002, 3002 is a dielectric material located inside 3108 as shown in Fig. 31B; Fig. 33, [0068, 0128]) on the substrate (202) and disposed between the first source/drain feature (an upper portion of 3212 above half the height 3116) and the second source/drain feature (an upper portion of 3214 above half the height 3116); and a continuous spacer (3108; [0136]) on the isolation feature (3002) and having a first portion (the left half of 3108) extending along the second sidewall surface (the right sidewall surface of an upper portion of 3212 above half the height 3116) and a second portion (the right half of 3108) extending along the third sidewall surface (the left sidewall surface of an upper portion of 3214 above half the height 3116), wherein, in a cross-sectional view (Fig. 34B) cut through both the first and second source/drain features (an upper portion of 3212 above half the height 3116 and an upper portion of 3214 above half the height 3116) and the isolation feature (3002), the continuous spacer (3108) spans a width less than a distance between the first source/drain feature and the second source/drain feature (a distance between the topmost points of an upper portion of 3212 above half the height 3116 and an upper portion of 3214 above half the height 3116).
Regarding clam 10, Ching et al. teach the semiconductor structure of claim 9, wherein both the first source/drain feature (an upper portion of 3212 above half the height 3116) and the second source/drain feature (an upper portion of 3214 above half the height 3116) are P-type source/drain features (the device can be used as a P-type metal-oxide-semiconductor (PMOS) ([0022]), while PMOS has P-type source/drain).
Regarding clam 11, Ching et al. teach the semiconductor structure of claim 9, further comprising: a first spacer (the left 3110; [0136]) extending along the first sidewall surface (the left sidewall surface of an upper portion of 3212 above half the height 3116) and adjacent to the first source/drain feature (an upper portion of 3212 above half the height 3116) in a first direction (the horizontal direction), wherein the first source/drain feature (an upper portion of 3212 above half the height 3116) further comprises a curved sidewall surface (the upper half of the left sidewall surface of an upper portion of 3212 above half the height 3116) over the first sidewall surface (the lower half of the left sidewall surface of an upper portion of 3212 above half the height 3116), the curved sidewall surface (the upper half of the left sidewall surface of an upper portion of 3212 above half the height 3116) curves outwardly towards the first direction (the horizontal direction).
Regarding clam 12, Ching et al. teach the semiconductor structure of claim 11, further comprising: a source/drain contact (1204B; [0079]) electrically coupled to the first source/drain feature (an upper portion of 3212 above half the height 3116), wherein the source/drain contact (1204B) is disposed adjacent to the first source/drain feature (an upper portion of 3212 above half the height 3116) along the first direction (the horizontal direction).
Allowable Subject Matter
Claims 15-20 are allowed.
Claims 2-7 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination, at least the limitations of "a source/drain contact disposed laterally adjacent to the dielectric layer and coupled to the source/drain feature" as recited in claim 2, “a dielectric layer having a lower portion lined by the continuous spacer and an upper portion in direct contact and over the first and second source/drain features” as recited in claim 13, and “a first source/drain contact over and electrically coupled to the first asymmetric source/drain feature; and a second source/drain contact over and electrically coupled to the second asymmetric source/drain feature, wherein a distance between the first source/drain contact and the second source/drain contact is greater than a distance between the first asymmetric source/drain feature and the second asymmetric source/drain feature” as recited in claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Basker et al. (US 9,324,870 B2) teach a FinFET having asymmetric source/drain regions.
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/HSIN YI HSIEH/Primary Examiner, Art Unit 2899 7/16/2026
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