DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed June 17, 2026 has been entered. Claims 1-20 remain pending in this application. Claims 1, 8-9, and 16-17 have been amended. No claims have been added. No new matter has been added.
In the Non-Final Office Action mailed March 20, 2026, Claims 8 and 16 were rejected under 35 U.S.C. § 112(b) for using the word ‘continued’ instead of ‘continuous.’ Applicant correctly notes the word ‘continued’ is not used in either claim. This was a typographical mistake on the part of the examiner. Claims 8 and 16 state, in relevant part: “[T]he adjusted analog bitline voltage is a continues voltage…” The word ‘continues’ was and remains incorrect and should properly read ‘continuous.’
Applicant’s amendments to the Specification, Drawings, and Claims have overcome each and every other objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed March 20, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “continues” in claims 8 and 16 is used by the claim to mean “continuous.” The term is indefinite because the specification does not clearly redefine the term. In the interest of compact prosecution, the word ‘continues’ will be read as ‘continuous’ in Claims 8 and 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,726,929 B1 to Xiang Yang (hereafter Yang) in view of US 2011/0080789 A1 to Pranav Kalavade, et al. (hereafter Kalavade) and further in view of US 2022/0180952 A1 to Jun Xu, et al., (hereafter Xu).
Regarding Amended Independent Claim 1, Yang discloses a memory device comprising:
A memory array comprising (A memory array: Yang, Figure 7):
a memory cell connected to a target wordline (A memory cell connected to a wordline: Yang, Figure 7); and
a first wordline adjacent to the target wordline (A wordline adjacent to the target wordline: Yang, Figure 7),
wherein the first wordline is to be programmed immediately subsequent to the target wordline (The adjacent wordline to be programmed subsequent to the target wordline: Yang, col.4:1-14); and
control logic (A controller 122: Yang, Figure 1),
operatively coupled with the memory array (Controller 122 coupled to the memory array 126: Yang, Figure 1),
identifying,
based on programming level information of the first wordline (Identifying the programming level voltage of the adjacent wordline: Yang, col.5:14-16),
a bitline voltage offset associated with the memory cell (Applying a bitline voltage offset as compensation: Yang, col.5:39-42); and
generating an adjusted bitline bias level by adjusting, using the bitline voltage offset, the fixed bitline bias (Bitline voltage offset adjusted to compensate for adjacent wordline programming: Yang, col.5:33-42); and
Yang discloses applying programming pulses to a target wordline associated with a memory cell (Yang, col.12:30-33) and verifying the programming level of the associated memory cell through verification checks (Yang, col.4:17-20). Yang fails to disclose comparing the verification voltage to a pre-determined threshold voltage meeting a threshold criterion or identifying a fixed bitline bias voltage associated with the memory cell. Kalavade, however, discloses a memory array wherein the programming operation includes performing operations comprising:
to perform operations comprising:
causing a first programming pulse (A first programming pulse: Kalavade, ¶[0019])
to be applied to the target wordline associated with the memory cell (The programming pulse applied to the word line associated with the memory cell: Kalavade, ¶[0019]);
causing a program verify operation (A program verify operation following the initial pulse: Kalavade, ¶[0019])
to be performed on the memory cell (The program verify operation performed on the memory cell: Kalavade, ¶[0019])
to verify programming of the memory cell (To verify programming of the memory cell: Kalavade, ¶[0019])
to a target programming level (Checking if the memory cell has a reached a pre-program voltage threshold (PPV): Kalavade, ¶[0028]);
determining that a measured threshold voltage of the memory cell satisfies a threshold criterion (Once the memory cell has reached the PPV: Kalavade, ¶[0028]);
identifying a fixed bitline bias level associated with the memory cell (Identifying a fixed bitline voltage for further programming pulses: Kalavade, ¶[0028]);
causing,
during applying a second programming pulse (During subsequent programming pulses: Kalavade, ¶[0028]),
an bitline voltage to be applied to the memory cell (Applying a bitline voltage to the bitline associated with the memory cell: Kalavade, 0028]),
wherein the bitline voltage is based on the adjusted bitline bias level (The applied bitline voltage being a predetermined voltage: Kalavade, ¶[0028]).
Kalavade teaches adjusting the bitline bias voltage helps achieve a tight Vt distribution without suffering a significant overall device programming time penalty (Kalavade, ¶[0015]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the aSSPC bitline voltage bias logic of Kalavade with the program disturb analysis of Yang, with a reasonable expectation of success. Both inventions are well known methods of narrowing Vt distributions in memory cells using bitline bias voltages and the combination of known inventions with predictable results is obvious and not patentable.
Neither Kalavade nor Yang disclose using an adjusted analog bitline voltage. Instead, each teaches a series of stepped bitline voltages. Xu, however, discloses using an adjusted analog bitline voltage (Disclosing using an analog bitline voltage: Xu, ¶[0018]). Xu teaches using an adjusted analog bitline voltage avoids the problems associated with using a fixed bitline voltage, such as program gate step, poison program noise, random sense noise, change change, etc. (Xu, ¶[0020]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the adjusted analog bitline voltage of Xu with the aSSPC bitline voltage bias logic of Kalavade, with a reasonable expectation of success. Both inventions are well known in the field of bitline bias voltages and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2 and the substantially similar limitations of Claims 10 and 18, Yang discloses the memory device of claim 1, wherein
the bitline voltage offset is specific to the target programming level (The bitline voltage compensation depends on the programming level of the target memory cell and the adjacent memory cell: Yang, col.5:25-32).
Regarding Claim 3 and the substantially similar limitations of Claims 11 and 19, Yang discloses the memory device of claim 1, wherein
the programming level information of the first wordline depends on a number of bits of information reflecting a threshold voltage of one or more aggressor memory cells of the first wordline (Disclosing a simplified approach where compensation is determined by a single bit or two bits: Yang, col.5:18-24).
Regarding Claim 4 and the substantially similar limitations of Claims 12 and 20, Yang discloses the memory device of claim 1, wherein
the bitline voltage offset is identified based on a data structure storing a plurality of bitline voltage offsets (Disclosing tables of compensation values: Yang, col.27:43-45),
each bitline voltage offset of the plurality of bitline voltage offsets corresponding to a programming level of the memory cell and a categorized programming level of the first wordline (Compensation values corresponding to a difference between the programming level of the target cell and the cell on the adjacent wordline: Yang, col.27:43-65; See Also, Yang, Figures 15A-15E).
Regarding Claim 5 and the substantially similar limitations of Claim 13, Kalavade discloses the memory device of claim 1, wherein causing the program verify operation to be performed on the memory cell to verify programming of the memory cell to the target programming level further comprises:
comparing the measured threshold voltage with a program verify threshold voltage level (Disclosing comparing the current programming voltage threshold to a pre-determined programming voltage: Kalavade, ¶[0036]).
Regarding Claim 6 and the substantially similar limitations of Claim 14, Kalavade discloses the memory device of claim 1, wherein determining that the measured threshold voltage of the memory cell satisfies the threshold criterion further comprises:
comparing the measured threshold voltage with a pre-verify threshold voltage level (Comparing the measured voltage threshold to a pre-determined voltage: Kalavade, ¶[0036]),
wherein the threshold criterion is satisfied responsive to that the measured threshold voltage is
larger than the pre-verify threshold voltage level (Wherein the threshold is higher than a predetermined level: Kalavade, ¶[0036]) and
smaller than a program verify threshold voltage level (The bitline voltage being increased to an inhibit voltage upon reaching the program threshold voltage: Kalavade, ¶[0035]).
Regarding Claim 7 and the substantially similar limitations of Claim 15, Yang discloses the memory device of claim 1, wherein
identifying the fixed bitline bias level associated with the memory cell is performed via a look-up operation of a stored or predetermined value (Disclosing tables of compensation values used to determine the bitline compensation bias: Yang, col.27:43-45).
Regarding Amended Claim 8 and the substantially similar limitations of Claim 16, Kalavade discloses the memory device of claim 1, wherein
the adjusted analog bitline voltage is a continuous voltage (Disclosing using an analog bitline voltage: Xu, ¶[0018])
starting from a ground voltage level until reaching the adjusted bitline bias level. (The bitline voltage increasing from ground to an adjusted bitline voltage level Vbl: Xu, Figure 5).
Regarding Amended Independent Claim 9, Yang discloses a method comprising:
causing, by a processing device (A processing controller: Yang, Figure 1) coupled with a memory array (Controller coupled with a memory array: Yang, Figure 1),
a first programming pulse (Applying a programming pulse to memory cells: Yang, col.12:30-33)
to be applied to a target wordline associated with a memory cell (Applying a programming pulse to memory cells: Yang, col.12:30-33),
wherein the memory array comprises the memory cell connected to the target wordline (A memory cell connected to a wordline: Yang, Figure 7) and
a first wordline adjacent to the target wordline (A wordline adjacent to the target wordline: Yang, Figure 7), and
wherein the first wordline is to be programmed immediately subsequent to the target wordline (The adjacent wordline to be programmed subsequent to the target wordline: Yang, col.4:1-14);
identifying,
based on programming level information of the first wordline (Identifying the programming level voltage of the adjacent wordline: Yang, col.5:14-16),
a bitline voltage offset associated with the memory cell (Applying a bitline voltage offset as compensation: Yang, col.5:39-42);
generating an adjusted bitline bias level by adjusting, using the bitline voltage offset, the fixed bitline bias (Bitline voltage offset adjusted to compensate for adjacent wordline programming: Yang, col.5:33-42).
Yang discloses verifying the programming level of the associated memory cell through verification checks (Yang, col.4:17-20). Yang fails to disclose comparing the verification voltage to a pre-determined threshold voltage meeting a threshold criterion or identifying a fixed bitline bias voltage associated with the memory cell. Kalavade, however, discloses a memory array wherein the programming operation includes performing operations comprising:
causing a program verify operation (A program verify operation following the initial pulse: Kalavade, ¶[0019])
to be performed on the memory cell (The program verify operation performed on the memory cell: Kalavade, ¶[0019])
to verify programming of the memory cell (To verify programming of the memory cell: Kalavade, ¶[0019])
to a target programming level (Checking if the memory cell has a reached a pre-program voltage threshold (PPV): Kalavade, ¶[0028]);
determining that a measured threshold voltage of the memory cell satisfies a threshold criterion (Once the memory cell has reached the PPV: Kalavade, ¶[0028]);
identifying a fixed bitline bias level associated with the memory cell (Identifying a fixed bitline voltage for further programming pulses: Kalavade, ¶[0028]);
causing,
during applying a second programming pulse (During subsequent programming pulses: Kalavade, ¶[0028]),
an adjusted analog bitline voltage (Disclosing using an analog bitline voltage: Xu, ¶[0018]) to be applied to the memory cell (Applying a bitline voltage to the bitline associated with the memory cell: Kalavade, 0028]),
wherein the bitline voltage is based on the adjusted bitline bias level (The applied bitline voltage being a predetermined voltage: Kalavade, ¶[0028]).
Kalavade teaches adjusting the bitline bias voltage helps achieve a tight Vt distribution without suffering a significant overall device programming time penalty (Kalavade, ¶[0015]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the aSSPC bitline voltage bias logic of Kalavade with the program disturb analysis of Yang, with a reasonable expectation of success. Both inventions are well known methods of narrowing Vt distributions in memory cells using bitline bias voltages and the combination of known inventions with predictable results is obvious and not patentable.
Neither Kalavade nor Yang disclose using an adjusted analog bitline voltage, each teaches a series of stepped bitline voltages. Xu, however, discloses using an adjusted analog bitline voltage (Disclosing using an analog bitline voltage: Xu, ¶[0018]). Xu teaches using an adjusted analog bitline voltage avoids the problems associated with using a fixed bitline voltage, such as program gate step, poison program noise, random sense noise, change change, etc. (Xu, ¶[0020]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the adjusted analog bitline voltage of Xu with the aSSPC bitline voltage bias logic of Kalavade, with a reasonable expectation of success. Both inventions are well known in the field of bitline bias voltages and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Amended Independent Claim 17, Yang discloses a non-transitory computer readable medium comprising
instructions (Instructions are inherent in a programming operation),
which when executed by a processing device (A processing controller: Yang, Figure 1) coupled with a memory array (Controller coupled with a memory array: Yang, Figure 1),
cause the processing device to perform operations comprising:
causing a first programming pulse (Applying a programming pulse to memory cells: Yang, col.12:30-33)
to be applied to a target wordline associated with a memory cell (Applying a programming pulse to memory cells: Yang, col.12:30-33),
wherein the memory array comprises the memory cell connected to the target wordline (A memory cell connected to a wordline: Yang, Figure 7) and
a first wordline adjacent to the target wordline (A wordline adjacent to the target wordline: Yang, Figure 7), and
wherein the first wordline is to be programmed immediately subsequent to the target wordline (The adjacent wordline to be programmed subsequent to the target wordline: Yang, col.4:1-14);
identifying,
based on programming level information of the first wordline (Identifying the programming level voltage of the adjacent wordline: Yang, col.5:14-16),
a bitline voltage offset associated with the memory cell (Applying a bitline voltage offset as compensation: Yang, col.5:39-42);
generating an adjusted bitline bias level by adjusting, using the bitline voltage offset, the fixed bitline bias (Bitline voltage offset adjusted to compensate for adjacent wordline programming: Yang, col.5:33-42).
Yang discloses verifying the programming level of the associated memory cell through verification checks (Yang, col.4:17-20). Yang fails to disclose comparing the verification voltage to a pre-determined threshold voltage meeting a threshold criterion or identifying a fixed bitline bias voltage associated with the memory cell. Kalavade, however, discloses a memory array wherein the programming operation includes performing operations comprising:
causing a program verify operation (A program verify operation following the initial pulse: Kalavade, ¶[0019])
to be performed on the memory cell (The program verify operation performed on the memory cell: Kalavade, ¶[0019])
to verify programming of the memory cell (To verify programming of the memory cell: Kalavade, ¶[0019])
to a target programming level (Checking if the memory cell has a reached a pre-program voltage threshold (PPV): Kalavade, ¶[0028]);
determining that a measured threshold voltage of the memory cell satisfies a threshold criterion (Once the memory cell has reached the PPV: Kalavade, ¶[0028]);
identifying a fixed bitline bias level associated with the memory cell (Identifying a fixed bitline voltage for further programming pulses: Kalavade, ¶[0028]);
causing,
during applying a second programming pulse (During subsequent programming pulses: Kalavade, ¶[0028]),
an adjusted analog bitline voltage to be applied to the memory cell (Applying a bitline voltage to the bitline associated with the memory cell: Kalavade, 0028]),
wherein the bitline (Disclosing using an analog bitline voltage: Xu, ¶[0018]) voltage is based on the adjusted bitline bias level (The applied bitline voltage being a predetermined voltage: Kalavade, ¶[0028]).
Kalavade teaches adjusting the bitline bias voltage helps achieve a tight Vt distribution without suffering a significant overall device programming time penalty (Kalavade, ¶[0015]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the aSSPC bitline voltage bias logic of Kalavade with the program disturb analysis of Yang, with a reasonable expectation of success. Both inventions are well known methods of narrowing Vt distributions in memory cells using bitline bias voltages and the combination of known inventions with predictable results is obvious and not patentable.
Neither Kalavade nor Yang disclose using an adjusted analog bitline voltage, each teaches a series of stepped bitline voltages. Xu, however, discloses using an adjusted analog bitline voltage (Disclosing using an analog bitline voltage: Xu, ¶[0018]). Xu teaches using an adjusted analog bitline voltage avoids the problems associated with using a fixed bitline voltage, such as program gate step, poison program noise, random sense noise, change change, etc. (Xu, ¶[0020]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the adjusted analog bitline voltage of Xu with the aSSPC bitline voltage bias logic of Kalavade, with a reasonable expectation of success. Both inventions are well known in the field of bitline bias voltages and the combination of known inventions with predictable results is obvious and not patentable.
Response to Arguments
Applicant's arguments filed June 17, 2026 have been fully considered but they are not persuasive.
There are appears to be a difference in understanding as to what was agreed during the telephonic interview conducted June 16, 2026. All parties seem to agree the key discussion centered on the Claim 1 limitation, “wherein the adjusted analog bitline voltage is based on the fixed bitline bias level adjusted by the bitline voltage offset." (Examiner Interview Summary, June 16, 2026). For clarity of the record, it is important to quote the key elements of both descriptions of that discussion.
Applicant describes the outcome of that discussion as follows: While no specific agreement was reached regarding allowability, the Examiner stated that "the fixed bitline bias level adjusted by the bitline voltage offset" seems to be not disclosed by the cited art subject to an updated search. (Applicant Arguments/Remarks, p.8 ¶6).
Examiner, however, describes that same conversation this way: 103 rejection based on primary art showing an adjustable bitline voltage and secondary art teaching adjusting programming parameters in anticipation of future programming operations. Applicant argued the combination was inappropriate as the secondary reference teaches adjusting the programmed threshold voltage while the instant application claims adjusting the programming bitline voltage itself. Examiners requested language clarifying the limitation. No agreement was reached, although the interview served to further examination, and any final determination of allowability would be dependent on precise wording of any amendment and be subject to additional analysis and search. (Examiner Interview Summary, June 16, 2026).
These descriptions clearly differ in the breadth of the agreed understanding. That said, Applicant's description is not inaccurate, just omitting key details. Yang clearly discloses adjusting the bitline voltage during a programming operation in anticipation of, and as compensation for, future programming of an adjacent wordline (Yang, col. 5:33-42). The critical difference is that Yang applies this offset to a stepped or staged bitline voltage, not an analog voltage as required by Claim 1. Newly cited art Xu, submitted in response to Applicant’s amendment, resolves this discrepancy.
Applicant’s remaining arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11,594,292 B2 to Scott A. Stoller, et al.: Disclosing applying a bitline bias voltage during a programming operation responsive to determining that a threshold voltage has been reached.
US 12,633,351 B2 to Yu-Chung Lien, et al.: Disclosing a memory system applying corrective programming convergence using neighbor wordline based analog bitline voltage offset.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER LANE REECE whose telephone number is (571)272-0288. The examiner can normally be reached Monday - Friday 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/UYEN SMET/Primary Examiner, Art Unit 2824
Prosecution Insights