DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because it exceeds 150 words in length. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “continued” in claims 8 and 16 is used by the claim to mean “continuous.” The term is indefinite because the specification does not clearly redefine the term. In the interest of compact prosecution, the word ‘continuous’ will be substituted in claims 8 and 16.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10,726,929 B1 to Xiang Yang (hereafter Yang) in view of US 2011/0080789 A1 to Pranav Kalavade, et al. (hereafter Kalavade).
Regarding Independent Claim 1, Yang discloses a memory device comprising:
A memory array comprising (A memory array: Yang, Figure 7):
a memory cell connected to a target wordline (A memory cell connected to a wordline: Yang, Figure 7); and
a first wordline adjacent to the target wordline (A wordline adjacent to the target wordline: Yang, Figure 7),
wherein the first wordline is to be programmed immediately subsequent to the target wordline (The adjacent wordline to be programmed subsequent to the target wordline: Yang, col.4:1-14); and
control logic (A controller 122: Yang, Figure 1),
operatively coupled with the memory array (Controller 122 coupled to the memory array 126: Yang, Figure 1),
identifying,
based on programming level information of the first wordline (Identifying the programming level voltage of the adjacent wordline: Yang, col.5:14-16),
a bitline voltage offset associated with the memory cell (Applying a bitline voltage offset as compensation: Yang, col.5:39-42); and
wherein the adjusted analog bitline voltage is
adjusted by the bitline voltage offset (Bitline voltage offset adjusted to compensate for adjacent wordline programming: Yang, col.5:33-42).
Yang discloses applying programming pulses to a target wordline associated with a memory cell (Yang, col.12:30-33) and verifying the programming level of the associated memory cell through verification checks (Yang, col.4:17-20). Yang fails to disclose comparing the verification voltage to a pre-determined threshold voltage meeting a threshold criterion or identifying a fixed bitline bias voltage associated with the memory cell. Kalavade, however, discloses a memory array wherein the programming operation includes performing operations comprising:
causing a first programming pulse (A first programming pulse: Kalavade, ¶[0019])
to be applied to the target wordline associated with the memory cell (The programming pulse applied to the word line associated with the memory cell: Kalavade, ¶[0019]);
causing a program verify operation (A program verify operation following the initial pulse: Kalavade, ¶[0019])
to be performed on the memory cell (The program verify operation performed on the memory cell: Kalavade, ¶[0019])
to verify programming of the memory cell (To verify programming of the memory cell: Kalavade, ¶[0019])
to a target programming level (Checking if the memory cell has a reached a pre-program voltage threshold (PPV): Kalavade, ¶[0028]);
determining that a measured threshold voltage of the memory cell satisfies a threshold criterion (Once the memory cell has reached the PPV: Kalavade, ¶[0028]);
identifying a fixed bitline bias level associated with the memory cell (Identifying a fixed bitline voltage for further programming pulses: Kalavade, ¶[0028]); and
causing,
during applying a second programming pulse (During subsequent programming pulses: Kalavade, ¶[0028]),
an adjusted analog bitline voltage to be applied to the memory cell (Applying a bitline voltage to the bitline associated with the memory cell: Kalavade, ¶[0028]),
wherein the adjusted analog bitline voltage is based on
the fixed bitline bias level (The applied bitline voltage being a predetermined voltage: Kalavade, ¶[0028]).
Kalavade teaches adjusting the bitline bias voltage helps achieve a tight Vt distribution without suffering a significant overall device programming time penalty (Kalavade, ¶[0015]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the aSSPC bitline voltage bias logic of Kalavade with the program disturb analysis of Yang, with a reasonable expectation of success. Both inventions are well known methods of narrowing Vt distributions in memory cells using bitline bias voltages and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 2 and the substantially similar limitations of Claims 10 and 18, Yang discloses the memory device of claim 1, wherein
the bitline voltage offset is specific to the target programming level (The bitline voltage compensation depends on the programming level of the target memory cell and the adjacent memory cell: Yang, col.5:25-32).
Regarding Claim 3 and the substantially similar limitations of Claims 11 and 19, Yang discloses the memory device of claim 1, wherein
the programming level information of the first wordline depends on a number of bits of information reflecting a threshold voltage of one or more aggressor memory cells of the first wordline (Disclosing a simplified approach where compensation is determined by a single bit or two bits: Yang, col.5:18-24).
Regarding Claim 4 and the substantially similar limitations of Claims 12 and 20, Yang discloses the memory device of claim 1, wherein
the bitline voltage offset is identified based on a data structure storing a plurality of bitline voltage offsets (Disclosing tables of compensation values: Yang, col.27:43-45),
each bitline voltage offset of the plurality of bitline voltage offsets corresponding to a programming level of the memory cell and a categorized programming level of the first wordline (Compensation values corresponding to a difference between the programming level of the target cell and the cell on the adjacent wordline: Yang, col.27:43-65; See Also, Yang, Figures 15A-15E).
Regarding Claim 5 and the substantially similar limitations of Claim 13, Kalavade discloses the memory device of claim 1, wherein causing the program verify operation to be performed on the memory cell to verify programming of the memory cell to the target programming level further comprises:
comparing the measured threshold voltage with a program verify threshold voltage level (Disclosing comparing the current programming voltage threshold to a pre-determined programming voltage: Kalavade, ¶[0036]).
Regarding Claim 6 and the substantially similar limitations of Claim 14, Kalavade discloses the memory device of claim 1, wherein determining that the measured threshold voltage of the memory cell satisfies the threshold criterion further comprises:
comparing the measured threshold voltage with a pre-verify threshold voltage level (Comparing the measured voltage threshold to a pre-determined voltage: Kalavade, ¶[0036]),
wherein the threshold criterion is satisfied responsive to that the measured threshold voltage is
larger than the pre-verify threshold voltage level (Wherein the threshold is higher than a predetermined level: Kalavade, ¶[0036]) and
smaller than a program verify threshold voltage level (The bitline voltage being increased to an inhibit voltage upon reaching the program threshold voltage: Kalavade, ¶[0035]).
Regarding Claim 7 and the substantially similar limitations of Claim 15, Yang discloses the memory device of claim 1, wherein
identifying the fixed bitline bias level associated with the memory cell is performed via a look-up operation of a stored or predetermined value (Disclosing tables of compensation values used to determine the bitline compensation bias: Yang, col.27:43-45).
Regarding Claim 8 and the substantially similar limitations of Claim 16, Kalavade discloses the memory device of claim 1, wherein
the adjusted analog bitline voltage is a continuous voltage (Disclosing a regular increase in applied bitline voltage for a series of pulses after passing the PPV: Kalavade, ¶[0036]; Note, Kalavade discloses particular increments rather than the smooth ramp illustrated by applicant as in Figure 5. This distinction is immaterial. Programming pulses are just that, pulses, and represent discrete points in time. Therefore, there is no difference in effect between a series of small steps versus a continuous ramp.)
starting from a ground voltage level until reaching a level that is the fixed bitline bias level reduced by the bitline voltage offset (The bitline voltage increasing from a neutral voltage to a maximum: Kalavade, Figure 3).
Regarding Independent Claim 9, Yang discloses a method comprising:
causing, by a processing device (A processing controller: Yang, Figure 1) coupled with a memory array (Controller coupled with a memory array: Yang, Figure 1),
a first programming pulse (Applying a programming pulse to memory cells: Yang, col.12:30-33)
to be applied to a target wordline associated with a memory cell (Applying a programming pulse to memory cells: Yang, col.12:30-33),
wherein the memory array comprises the memory cell connected to the target wordline (A memory cell connected to a wordline: Yang, Figure 7) and
a first wordline adjacent to the target wordline (A wordline adjacent to the target wordline: Yang, Figure 7), and
wherein the first wordline is to be programmed immediately subsequent to the target wordline (The adjacent wordline to be programmed subsequent to the target wordline: Yang, col.4:1-14);
identifying,
based on programming level information of the first wordline (Identifying the programming level voltage of the adjacent wordline: Yang, col.5:14-16),
a bitline voltage offset associated with the memory cell (Applying a bitline voltage offset as compensation: Yang, col.5:39-42); and
wherein the adjusted analog bitline voltage is based on
adjusted by the bitline voltage offset (Bitline voltage offset adjusted to compensate for adjacent wordline programming: Yang, col.5:33-42).
Yang discloses verifying the programming level of the associated memory cell through verification checks (Yang, col.4:17-20). Yang fails to disclose comparing the verification voltage to a pre-determined threshold voltage meeting a threshold criterion or identifying a fixed bitline bias voltage associated with the memory cell. Kalavade, however, discloses a memory array wherein the programming operation includes performing operations comprising:
causing a program verify operation (A program verify operation following the initial pulse: Kalavade, ¶[0019])
to be performed on the memory cell (The program verify operation performed on the memory cell: Kalavade, ¶[0019])
to verify programming of the memory cell (To verify programming of the memory cell: Kalavade, ¶[0019])
to a target programming level (Checking if the memory cell has a reached a pre-program voltage threshold (PPV): Kalavade, ¶[0028]);
determining that a measured threshold voltage of the memory cell satisfies a threshold criterion (Once the memory cell has reached the PPV: Kalavade, ¶[0028]);
identifying a fixed bitline bias level associated with the memory cell (Identifying a fixed bitline voltage for further programming pulses: Kalavade, ¶[0028]); and
causing,
during applying a second programming pulse (During subsequent programming pulses: Kalavade, ¶[0028]),
an adjusted analog bitline voltage to be applied to the memory cell (Applying a bitline voltage to the bitline associated with the memory cell: Kalavade, ¶[0028]),
wherein the adjusted analog bitline voltage is based on
the fixed bitline bias level (The applied bitline voltage being a predetermined voltage: Kalavade, ¶[0028]).
Kalavade teaches adjusting the bitline bias voltage helps achieve a tight Vt distribution without suffering a significant overall device programming time penalty (Kalavade, ¶[0015]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the aSSPC bitline voltage bias logic of Kalavade with the program disturb analysis of Yang, with a reasonable expectation of success. Both inventions are well known methods of narrowing Vt distributions in memory cells using bitline bias voltages and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Independent Claim 17, Yang discloses a non-transitory computer readable medium comprising
instructions (Instructions are inherent in a programming operation),
which when executed by a processing device (A processing controller: Yang, Figure 1) coupled with a memory array (Controller coupled with a memory array: Yang, Figure 1),
cause the processing device to perform operations comprising:
causing a first programming pulse (Applying a programming pulse to memory cells: Yang, col.12:30-33)
to be applied to a target wordline associated with a memory cell (Applying a programming pulse to memory cells: Yang, col.12:30-33),
wherein the memory array comprises the memory cell connected to the target wordline (A memory cell connected to a wordline: Yang, Figure 7) and
a first wordline adjacent to the target wordline (A wordline adjacent to the target wordline: Yang, Figure 7), and
wherein the first wordline is to be programmed immediately subsequent to the target wordline (The adjacent wordline to be programmed subsequent to the target wordline: Yang, col.4:1-14);
identifying,
based on programming level information of the first wordline (Identifying the programming level voltage of the adjacent wordline: Yang, col.5:14-16),
a bitline voltage offset associated with the memory cell (Applying a bitline voltage offset as compensation: Yang, col.5:39-42); and
wherein the adjusted analog bitline voltage is based on
adjusted by the bitline voltage offset (Bitline voltage offset adjusted to compensate for adjacent wordline programming: Yang, col.5:33-42).
Yang discloses verifying the programming level of the associated memory cell through verification checks (Yang, col.4:17-20). Yang fails to disclose comparing the verification voltage to a pre-determined threshold voltage meeting a threshold criterion or identifying a fixed bitline bias voltage associated with the memory cell. Kalavade, however, discloses a memory array wherein the programming operation includes performing operations comprising:
causing a program verify operation (A program verify operation following the initial pulse: Kalavade, ¶[0019])
to be performed on the memory cell (The program verify operation performed on the memory cell: Kalavade, ¶[0019])
to verify programming of the memory cell (To verify programming of the memory cell: Kalavade, ¶[0019])
to a target programming level (Checking if the memory cell has a reached a pre-program voltage threshold (PPV): Kalavade, ¶[0028]);
determining that a measured threshold voltage of the memory cell satisfies a threshold criterion (Once the memory cell has reached the PPV: Kalavade, ¶[0028]);
identifying a fixed bitline bias level associated with the memory cell (Identifying a fixed bitline voltage for further programming pulses: Kalavade, ¶[0028]); and
causing,
during applying a second programming pulse (During subsequent programming pulses: Kalavade, ¶[0028]),
an adjusted analog bitline voltage to be applied to the memory cell (Applying a bitline voltage to the bitline associated with the memory cell: Kalavade, ¶[0028]),
wherein the adjusted analog bitline voltage is based on
the fixed bitline bias level (The applied bitline voltage being a predetermined voltage: Kalavade, ¶[0028]).
Kalavade teaches adjusting the bitline bias voltage helps achieve a tight Vt distribution without suffering a significant overall device programming time penalty (Kalavade, ¶[0015]). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the aSSPC bitline voltage bias logic of Kalavade with the program disturb analysis of Yang, with a reasonable expectation of success. Both inventions are well known methods of narrowing Vt distributions in memory cells using bitline bias voltages and the combination of known inventions with predictable results is obvious and not patentable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 11,594,292 B2 to Scott A. Stoller, et al.: Disclosing applying a bitline bias voltage during a programming operation responsive to determining that a threshold voltage has been reached.
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/CHRISTOPHER LANE REECE/ Examiner, Art Unit 2824
/UYEN SMET/ Primary Examiner, Art Unit 2824