DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
This is a response to the amendment filed 4/8/2026. Claims 2-4 are pending and are under examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Tsai et al. (US 2010/0150302) in view of Shimizu et al. (US 2011/0001747).
Regarding claim 2, Tsai et al.’s figure 4 A display device comprising: a scan line driver circuit including a first transistor (T2), a second transistor (T13), a third transistor (T6), a fourth transistor (T12), a fifth transistor (transistor receives input signal IN7/), and a sixth transistor (transistor receives input signal IN8/); wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, wherein one of a source and a drain of the first transistor (T2) is electrically connected to a first wiring (IN1/), wherein the other of the source and the drain of the first transistor (T2) is electrically connected to a second wiring (OUT1/), wherein one of a source and a drain of the second transistor (T13) is electrically connected to a third wiring (wire connects to Vss), wherein the other of the source and the drain of the second transistor (T13) is electrically connected to the second wiring (OUT1/), wherein one of a source and a drain of the third transistor (T6) is electrically connected to a gate of the first transistor (T2) , wherein the other of the source and the drain of the third transistor (T6) is electrically connected to the other of the source and the drain of the first transistor (T2), wherein a gate of the third transistor (T6) is electrically connected to a fourth wiring (IN2/), wherein one of a source and a drain of the fourth transistor (T12) is electrically connected to the third wiring (T13 and T12 are coupled together to the same wiring), wherein the other of the source and the drain of the fourth transistor (T12) is electrically connected to the gate of the first transistor (T2), wherein a gate of the fourth transistor (T12) is electrically connected to a gate of the second transistor (T13), wherein one of a source and a drain of the fifth transistor (transistor receives IN7/) is electrically connected to a fifth wiring (wire connected to the transistor), wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor (T2), wherein one of a source and a drain of the sixth transistor (transistor receives input signal IN8/) is electrically connected to the fifth wiring, wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor (T2), wherein a first signal (CK1) is input to the first wiring, wherein a second signal (CK2) is input to the fourth wiring, wherein the first signal is different from the second signal, and wherein the second wiring is a scan line (On).
Tsai et al. discloses each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor as amorphous silicon thin film transistor instead of each transistor includes oxide semiconductor in a channel region as called for in claim 2.
Shimizu et al.’s paragraph 0003 teaches that a TFT in which an amorphous oxide semiconductor (called an AOS hereinafter) is used as its channel layer has mobility which is ten times or more as much as that of an a-Si TFT. Therefore, it would have been obvious to person skilled in the art at the time the invention was made to have Tsai et al.’s transistors includes oxide semiconductor in a channel region for the purpose of increasing speed as taught by Shimizu et al. reference.
Regarding claim 3, Tsai et al.’s figure 4 A display device comprising: a scan line driver circuit including a first transistor (T2), a second transistor (T13), a third transistor (T6), a fourth transistor (T12), a fifth transistor (transistor receives input signal IN7/), and a sixth transistor (transistor receives input signal IN8/); wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, wherein one of a source and a drain of the first transistor (T2) is electrically connected to a first wiring (IN1/), wherein the other of the source and the drain of the first transistor (T2) is electrically connected to a second wiring (OUT1/), wherein one of a source and a drain of the second transistor (T13) is electrically connected to a third wiring (wire connects to Vss), wherein the other of the source and the drain of the second transistor (T13) is electrically connected to the second wiring (OUT1/), wherein one of a source and a drain of the third transistor (T6) is electrically connected to a gate of the first transistor (T2) , wherein the other of the source and the drain of the third transistor (T6) is electrically connected to the other of the source and the drain of the first transistor (T2), wherein a gate of the third transistor (T6) is electrically connected to a fourth wiring (IN2/), wherein one of a source and a drain of the fourth transistor (T12) is electrically connected to the third wiring (T13 and T12 are coupled together to the same wiring), wherein the other of the source and the drain of the fourth transistor (T12) is electrically connected to the gate of the first transistor (T2), wherein a gate of the fourth transistor (T12) is electrically connected to a gate of the second transistor (T13), wherein one of a source and a drain of the fifth transistor (transistor receives IN7/) is electrically connected to a fifth wiring (wire connected to the transistor), wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor (T2), wherein one of a source and a drain of the sixth transistor (transistor receives input signal IN8/) is electrically connected to the fifth wiring, wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor (T2), wherein a first signal (CK1) is input to the first wiring, wherein a second signal (CK2) is input to the fourth wiring, wherein the first signal is different from the second signal, and wherein the second wiring is a scan line (On) and wherein a W/L (channel width/channel length) ratio of the fifth transistor is approximately equal to a W/L ratio of the sixth transistor (W/L of the fifth and sixth transistors are assumed to equal unless stated otherwise by the reference).
Tsai et al. discloses each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor as amorphous silicon thin film transistor instead of each transistor includes oxide semiconductor in a channel region as called for in claim 3.
Shimizu et al.’s paragraph 0003 teaches that a TFT in which an amorphous oxide semiconductor (called an AOS hereinafter) is used as its channel layer has mobility which is ten times or more as much as that of an a-Si TFT. Therefore, it would have been obvious to person skilled in the art at the time the invention was made to have Tsai et al.’s transistors includes oxide semiconductor in a channel region for the purpose of increasing speed as taught by Shimizu et al. reference.
Regarding claim 4, Tsai et al.’s figure 4 shows a display device comprising Tsai et al.’s figure 4 A display device comprising: a scan line driver circuit including a first transistor (T2), a second transistor (T13), a third transistor (T6), a fourth transistor (T12), a fifth transistor (transistor receives input signal IN7/), and a sixth transistor (transistor receives input signal IN8/); wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor, wherein one of a source and a drain of the first transistor (T2) is electrically connected to a first wiring (IN1/), wherein the other of the source and the drain of the first transistor (T2) is electrically connected to a second wiring (OUT1/), wherein one of a source and a drain of the second transistor (T13) is electrically connected to a third wiring (wire connects to Vss), wherein the other of the source and the drain of the second transistor (T13) is electrically connected to the second wiring (OUT1/), wherein one of a source and a drain of the third transistor (T6) is electrically connected to a gate of the first transistor (T2) , wherein the other of the source and the drain of the third transistor (T6) is electrically connected to the other of the source and the drain of the first transistor (T2), wherein a gate of the third transistor (T6) is electrically connected to a fourth wiring (IN2/), wherein one of a source and a drain of the fourth transistor (T12) is electrically connected to the third wiring (T13 and T12 are coupled together to the same wiring), wherein the other of the source and the drain of the fourth transistor (T12) is electrically connected to the gate of the first transistor (T2), wherein a gate of the fourth transistor (T12) is electrically connected to a gate of the second transistor (T13), wherein one of a source and a drain of the fifth transistor (transistor receives IN7/) is electrically connected to a fifth wiring (wire connected to the transistor), wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor (T2), wherein one of a source and a drain of the sixth transistor (transistor receives input signal IN8/) is electrically connected to the fifth wiring, wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor (T2), wherein a first signal (CK1) is input to the first wiring, wherein a second signal (CK2) is input to the fourth wiring, wherein the first signal is different from the second signal.
Tsai et al. reference does not show: (1) each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor includes oxide semiconductor in a channel region; (2) a W/L (channel width/channel length) ratio of the second transistor is larger than a W/L ratio of the fourth transistor as called for in claim 4.
Regarding the difference noted in item (1), Shimizu et al.’s paragraph 0003 teaches that a TFT in which an amorphous oxide semiconductor (called an AOS hereinafter) is used as its channel layer has mobility which is ten times or more as much as that of an a-Si TFT. Therefore, it would have been obvious to person skilled in the art at the time the invention was made to have Tsai et al.’s transistors includes oxide semiconductor in a channel region for the purpose of increasing speed as taught by Shimizu et al. reference.
Regarding the difference noted in item (2), it is commonly known in the art that a larger W/L ratio increases current flow and device speed, while a smaller W/L ratio reduces current and can minimize short-channel effects like DIBL and HCI. The optimal ratio depends on the desired application, technology node, and the need to balance performance with factors like power consumption and reliability. In this instant, the second transistor (T13) is connected between the scan line and the ground. Thus, enhancing its W/L ratio would be desired in bringing/pulling the output signal down at a higher speed. Therefore, outside of any non-obvious results, the obviousness of having the second transistor W/L ratio larger will not be patentable under 35USC 103.
Conclusion
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/TUAN T LAM/Primary Examiner, Art Unit 2842 5/18/2026
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