Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1-3, 5-10, 12-16, 18-20, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noack (Pub. No.: US 2019/0325963).
3. Regarding independent claim 1, Noack teaches a memory device (Fig. 5), comprising: a plurality of memory units (Fig. 5, #500c) arranged in rows (Fig. 5, along #503-1 direction), columns (Fig. 5, along #501-m direction), and pages (Fig. 5, #503-1); a plurality of word lines (Fig. 5, #504-1 for example) extending along the rows (Fig. 5, along #503-1 direction) and extending in parallel to a first direction (Fig. 5, along #503-1 direction) ; and a plurality of match lines (Fig. 5, #502-m for example) extending along the columns (Fig. 5, along #501-m direction) and extending in parallel to a second direction (Fig. 5, along #501-m direction) that is perpendicular (see Fig. 5) to the first direction (Fig. 5, along #503-1 direction); and wherein the pages (Fig. 5, #503-1) extend in the first direction (Fig. 5, along #503-1 direction).
4. Regarding claim 9, Noack teaches a first ferroelectric layer (Fig. 3A, #112a) between a first word line (Fig. 3A, #204a) of the plurality of word lines (Fig. 5, #504-1 for example) and a first match line (Fig. 3A, #202a) of the plurality of match lines (see Fig. 5).
5. Regarding claim 10, Noack teaches a first transistor (see Fig. 3, #112a) having a source terminal (Fig. 3, #202a) and a drain terminal (Fig. 3, #202b); and a second transistor (Fig. 3, #112b) sharing the source terminal (Fig. 3, #202a) and drain terminal of the first transistor, the source terminal (Fig. 3, #202a) and the drain terminal (Fig. 3, #202b) connected to a match line (Fig. 5, #502-m) of the plurality of match lines (Fig. 5, #502-m).
6. Regarding claim 11, Noack teaches the first transistor (see Fig. 3, #112a) comprises a channel layer (see Fig. 3, #112a), and wherein the second transistor (Fig. 3, #112b) comprises a channel layer (see Fig. 3, #112ab), and wherein the channel layer (see Fig. 3, #112a) of the first transistor (see Fig. 3, #112a) is spaced (see Fig. 3a) from the channel layer of the second transistor (Fig. 3, #112b).
7. Regarding claim 12, Noack teaches a memory unit (Fig. 3a) of the plurality of memory units (Fig. 5, #500c) is configured to store ternary data (see Fig. 5a).
8. Regarding claim 13, Noack teaches data states of the plurality of memory units (Fig. 5, #500c) can be searched (see Fig. 5) by applying a signal to the plurality of word lines (Fig. 5, #504-1 for example).
9. Regarding claim 14, Noack teaches a memory unit of the plurality of memory units (Fig. 5, #500c) comprises a first transistor (see Fig. 3, #112a) and a second transistor (Fig. 3, #112b) each having channels that are separated by a width of a match line (Fig. 5, #502-m for example) of the plurality of match lines (Fig. 5, #502-m for example).
Allowable Subject Matter
10. Claims 1-7, 15-20 are allowed.
11. With respect to independent claims 1, there is no teaching, suggestion, or motivation for combination in the prior art to a first ferroelectric layer disposed between the first word line and the match line; a first channel layer disposed between the first ferroelectric layer and the match line; a second ferroelectric layer disposed between the second word line and the match line; and a second channel layer disposed between the first ferroelectric layer and the match line.
12. With respect to dependent claims 2-7, since these claims are depending on claim 1, therefore claims 2-7 are allowable subject matter.
13. With respect to independent claims 15, there is no teaching, suggestion, or motivation for combination in the prior art to a first ferroelectric layer disposed between the inner sidewall of the first word line and a first side of the first source and first drain; and a first channel layer disposed between an inner sidewall of the first ferroelectric layer and the first side of the first source and the first drain.
14. With respect to dependent claims 16-20, since these claims are depending on claim 15, therefore claims 16-20 are allowable subject matter.
Conclusion
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, YU et al (Pub. No.: US 2021/0142837A1).
YU et al (Pub. No.: US 2021/0142837A1) shows ferroelectric transistors.
16. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Han Yang whose telephone is (571) 270-3048. The examiner can normally be reached on Monday-Friday 8am-5pm with alternate Friday off. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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HY
02/04/2026
/HAN YANG/
Primary Examiner, Art Unit 2824