Prosecution Insights
Last updated: August 18, 2026
Application No. 18/785,748

DATA TRANSMISSION POWER OPTIMIZATION

Non-Final OA §103
Filed
Jul 26, 2024
Priority
Aug 24, 2022 — divisional of 12/130,758
Examiner
LEE, CHUN KUAN
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Qualcomm Incorporated
OA Round
3 (Non-Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
1y 3m
Est. Remaining
72%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
465 granted / 681 resolved
+13.3% vs TC avg
Minimal +4% lift
Without
With
+3.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
19 currently pending
Career history
708
Total Applications
across all art units

Statute-Specific Performance

§101
2.5%
-37.5% vs TC avg
§103
73.5%
+33.5% vs TC avg
§102
5.3%
-34.7% vs TC avg
§112
8.1%
-31.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 681 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . CONTINUED EXAMINATION UNDER 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/15/2026 has been entered. RESPONSE TO ARGUMENTS Applicant's arguments filed 5/15/2026 have been fully considered but they are not persuasive. In response to applicant's argument, regarding independent claim 13, that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., claimed features associated with “first lane” and the “second lane” are coupled to the “first bus interface” and to “the second bus interface,” and that the “crossbar” is configured to transfer the “second packet” and the “first packet” during overlapping "consecutive clock cycles.”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). In response to applicant’s arguments with regard to the independent claim 13 rejected under 35 U.S.C. 103(a) that the combination of the references does not teach/suggest the claimed feature “… lanes in a communication bus … configured to transfer packets from a second bus interface to the first bus interface …” because Sindhu does not teach the above claimed features; applicant's arguments have fully been considered, but are not found to be persuasive. The examiner respectfully disagrees, and to further clarify, by combining Sindhu’s being coupled to a plurality of lanes in a bus, wherein each of the plurality of lanes in the bus operating accordingly (e.g. associated with communication paths of output ports (108) in Fig. 2B) (Fig. 2B; and col. 4, ll. 14-51) with Smith’s first bus interface configured to be coupled to a communication bus, wherein the communication bus is configure to transfer packets from a second bus interface to the first bus interface (e.g. associated with communication bus for transferring data packet between MOCB crossbar’s interface to local SoC device and MOCB crossbar’s interface to nonlocal Soc Device: Fig. 2A-2B; col. 6, l. 41 to col. 8, l. 42) (Fig. 2A-2B; Fig. 4A-4B; col. 6, l. 41 to col. 9, l. 49; and col. 10, ll. 1-59), the resulting combination of the references would further teach/suggest the above claimed features. I. ALLOWABLE SUBJECT MATTER Claims 1-2, 4-6, 8-9, and 12 are allowed. II. REJECTIONS BASED ON PRIOR ART Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 13 are rejected under 35 U.S.C. 103 as being unpatentable over Smith et al. (US Patent 10,015,087) in view of Sindhu et al. (US Patent 5,905,725). As per claim 13, Smith teaches/suggests an integrated circuit (IC), comprising: a first bus interface configured to be coupled to a communication bus, wherein the communication bus is configure to transfer packets from a second bus interface to the first bus interface (e.g. associated with communication bus for transferring data packet between MOCB crossbar’s interface to local SoC device and MOCB crossbar’s interface to nonlocal Soc Device: Fig. 2A-2B; col. 6, l. 41 to col. 8, l. 42); and a crossbar (e.g. associated with MOCB Crossbar (108)) coupled to the bus interface and configured to: receive data; and route to a first memory (e.g. associated with write command which writes to a given address of corresponding storage/memory: col. 8, ll. 33-66), being coupled to the first bus interface and the second bus interface (e.g. associated with MOCB crossbar’s interface to nonlocal Soc Device and MOCB crossbar’s interface to local SoC device) (Fig. 2A-2B; Fig. 4A-4B; col. 6, l. 41 to col. 9, l. 49; and col. 10, ll. 1-59). Smith does not teach the IC comprising: being coupled to a plurality of lanes in a bus, wherein each of the plurality of lanes in the bus operating accordingly; having a first packet from a first lane; read a channel identifier in the first packet; and route the first packet based on the channel identifier, wherein each lane of the plurality of lanes consists of a physical electrical conductor electrically coupled. Sindhu teaches/suggests a system comprising: being coupled to a plurality of lanes in a bus, wherein each of the plurality of lanes in the bus operating accordingly (e.g. associated with communication paths of output ports (108) in Fig. 2B); having a first packet from a first lane (e.g. associated with receiving packet at an input port (107): col. 4, ll. 30-51); read a channel identifier in the first packet (e.g. associated with reading key from packet: col. 4, ll. 30-51); and route the first packet based on the channel identifier (e.g. associated with forwarding the packet to output port (180) based on key: col. 4, ll. 30-51), wherein each lane of the plurality of lanes consists of a physical electrical conductor electrically coupled (e.g. associated with port(s) being physical that would have conducted electrical signal when communicating packet(s)) (Fig. 2B; and col. 4, ll. 14-51). It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Sindhu’s data transferring architecture into Smith’s IC for the benefit of implementing an architecture that efficiently manage and route packets (Sindhu, col. 2, ll. 66-67) to obtain the invention as specified in claim 13. II. PERTINENT RELATED PRIOR ART Srinivasan et al. (US Pub.: 2016/0173365): discloses a crossbar switch that can be configured to simultaneously send packets from each input to each possible output III. CLOSING COMMENTS CONCLUSION STATUS OF CLAIMS IN THE APPLICATION The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i): CLAIMS REJECTED IN THE APPLICATION Per the instant office action, claims 1-2, 4-6, 8-9, and 12-13 have received a first action on the merits and are subject of a first action non-final. DIRECTION OF FUTURE CORRESPONDENCES Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday. IMPORTANT NOTE If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHUN KUAN LEE/Primary Examiner Art Unit 2181 June 05, 2026
Read full office action

Prosecution Timeline

Jul 26, 2024
Application Filed
Sep 25, 2025
Non-Final Rejection mailed — §103
Dec 17, 2025
Response Filed
Feb 17, 2026
Final Rejection mailed — §103
Apr 13, 2026
Response after Non-Final Action
May 15, 2026
Request for Continued Examination
May 19, 2026
Response after Non-Final Action
Jun 09, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12665782
PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD
3y 4m to grant Granted Jun 23, 2026
Patent 12650941
METHOD AND RELATED APPARATUS FOR PCIE DATA TRANSMISSION
1y 8m to grant Granted Jun 09, 2026
Patent 12645195
METHOD FOR GENERATING A TWIN SENSOR BY WAY OF PARAMETER INHERITANCE
3y 3m to grant Granted Jun 02, 2026
Patent 12639235
CROSS-DOMAIN VOLTAGE BUS RESOURCE SHARING FOR IMPROVED POWER DELIVERY NETWORK
2y 9m to grant Granted May 26, 2026
Patent 12639237
MEMORY DEVICE WITH INTERNAL PROCESSING INTERFACE
1y 9m to grant Granted May 26, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
72%
With Interview (+3.8%)
3y 4m (~1y 3m remaining)
Median Time to Grant
High
PTA Risk
Based on 681 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month