DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claims 5, 12, 15 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to claim 5, the prior art fails to teach in combination with the rest of the limitations in the claim: “wherein the time-to-voltage converter circuit includes an amplifier circuit, a capacitor coupled between an output of the amplifier circuit and an input of the
amplifier circuit, and a resistor coupled between the input of the amplifier circuit and a switch, and wherein to generate the sample signal, the time-to-voltage converter circuit is further configured to:
set the sample signal to the reference voltage during a reset period; and change, during an integration period, the sample signal by an amount proportional to a reciprocal of a product of a first value of the capacitor and a second value of the resistor.”
With respect to claim 12, the prior art fails to teach in combination with the rest of the limitations in the claim: “wherein the time-to-voltage converter circuit includes an amplifier circuit, a capacitor coupled between an output of the amplifier circuit and an input of the amplifier circuit, and a resistor coupled between the input of the amplifier circuit and a switch, and wherein generating the sample signal includes:
setting the first voltage level of the sample signal to the reference voltage during a reset period; and
decreasing, during the period of time the clock signal is at the particular logic value, the first voltage level of the sample signal by an amount proportional to a reciprocal of a product of a first value of the capacitor and a second value of the resistor.”
With respect to claim 15, the prior art fails to teach in combination with the rest of the limitations in the claim: “wherein the jitter sensor circuit includes an analog-to-digital converter circuit that includes a capacitor, and wherein to generate the output signal, the jitter sensor circuit is further configured to:
charge the capacitor using the reference voltage during a first time period; decouple the capacitor from the reference voltage during a second time period; and generate the output signal using a second voltage level of the capacitor during the second time period.”
With respect to claim 19, the prior art fails to teach in combination with the rest of the limitations in the claim: “wherein the jitter sensor circuit includes a time-to-voltage converter circuit that includes an amplifier circuit, a capacitor coupled between an output of the amplifier circuit and an input of the amplifier circuit, and a resistor coupled between the input of the amplifier circuit and a switch, and wherein to generate the sample signal, the jitter sensor circuit is further configured to:
set the first voltage level of the sample signal to the reference voltage during a reset period; and
decrease, during the period of time the clock signal is at the particular logic value, the first voltage level of the sample signal by an amount proportional to a reciprocal of a product of a first value of the capacitor and a second value of the resistor.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-11, 13, 14, 16-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maltabas et al. (U.S. Patent No. 11,031,945 B1).
With respect to claim 1, Maltabas et al. discloses an apparatus, comprising: a reference circuit configured to generate a reference voltage using a power supply voltage (delay adjustment signal 206 Fig. 2; this adjusts a power supply voltage); a time-to-voltage converter circuit (see time-to-digital converter circuit 103 shown in Fig. 1) configured, in response to being activated, to generate a sample signal using the reference voltage (see sample circuit 302 shown in Fig. 3), wherein a first voltage level of the sample signal is proportional to a portion of a period of a clock signal (col. 3, lines 42-55); a control circuit configured to activate the time-to-voltage converter circuit at a plurality of time points (see time-to-digital converter circuit 103 shown in Fig. 1); and an analog-to-digital converter circuit configured to generate (col. 3, lines 35-41), using the reference voltage, an output signal based on the sample signal, wherein the output signal includes a plurality of bits whose value is indicative of the period of time the clock signal is the particular logic value (col. 5, lines 49-55).
With respect to claim 2, Maltabas et al. discloses the apparatus of claim 1, wherein to generate the output signal, the analog-to-digital converter circuit (see time-to-digital converter circuit 103 shown in Fig. 1) is further configured to:
charge a capacitor using the reference voltage during a first time period (col. 5, lines 55-col. 6, lines 5); decouple the capacitor from the reference voltage during a second time period (col. 6, lines 66-col. 7, line 6); and generate the output signal using a second voltage level of the capacitor during the second time period (col. 7, lines 23-33).
With respect to claim 3, Maltabas et al. discloses the apparatus of claim 1, wherein to generate the output signal, the analog-to-digital converter circuit is further configured to offset the sample signal using the reference voltage (col. 4, lines 8-17).
With respect to claim 4, Maltabas et al. discloses the apparatus of claim 1, wherein to generate the output signal, the analog-to-digital converter circuit is configured to: convert the output signal to a feedback voltage using the reference voltage (see time-to-digital converter circuit 103 shown in Fig. 1); perform a comparison of the feedback voltage to the sample signal (col. 10, lines 53-60); and adjust the output signal using a result of the comparison (col. 10, lines 61-67).
With respect to claim 6, Maltabas et al. the apparatus of claim 1, wherein to activate the time-to-voltage converter circuit at a plurality of time points (see time-to-digital converter circuit 103 shown in Fig. 1), the control circuit is further configured to wait a random time period between a first activation of the time-to-voltage converter circuit and a second activation of the time-to-voltage converter circuit (delay adjustment signal 206 Fig. 2; this adjusts a power supply voltage).
With respect to claim 7, Maltabas et al. discloses a method, comprising:
generating, by a reference circuit, a reference voltage using a power supply voltage (delay adjustment signal 206 Fig. 2; this adjusts a power supply voltage); generating, by a time-to-voltage converter circuit in response to being activated, a sample signal using the reference voltage (see time-to-digital converter circuit 103 shown in Fig. 1), wherein a first voltage level of the sample signal is proportional to a period of time a clock signal is at a particular logic value (col. 5, lines 49-55);
activating, by a control circuit, the time-to-voltage converter circuit at a plurality of time points (delay adjustment signal 206 Fig. 2; this adjusts a power supply voltage); and generating, by an analog-to-digital converter circuit using the reference voltage (col. 10, lines 61-67), an output signal based on the sample signal, wherein the output signal includes a plurality of bits whose value is indicative of the period of time the clock signal is the particular logic value (col. 5, lines 49-55).
With respect to claim 8, Maltabas et al. discloses the method of claim 7, wherein generating the output signal includes: charging, by the analog-to-digital converter circuit (col. 10, lines 61-67), a capacitor using the reference voltage during a first time period (col. 4, lines 8-17);
decoupling, by the analog-to-digital converter circuit, the capacitor from the reference voltage during a second time period (col. 11, lines 3-10); and
generating, by the analog-to-digital converter circuit, the output signal using a second voltage level of the capacitor during the second time period (col. 11, lines 30-38).
With respect to claim 9, Maltabas et al. discloses the method of claim 7, further comprising offsetting, by the analog-to-digital converter circuit, the sample signal using the reference voltage (col. 3, lines 21-31).
With respect to claim 10, Maltabas et al. discloses the method of claim 7, wherein generating the output signal includes: converting the output signal to a feedback voltage using the reference voltage; performing a comparison of the feedback voltage to the sample signal (col. 15, lines 30-40); and adjusting the output signal using a result of the comparison (col. 8, lines 42-47).
With respect to claim 11, Maltabas et al. discloses the method of claim 10, wherein the analog-to-digital converter circuit includes a plurality of capacitors whose respective first terminals are coupled to an input node (col. 10, lines 61-67), and wherein converting the output signal to the feedback voltage includes coupling respective second terminals of the plurality of capacitors to the reference voltage based on values of corresponding bits of the plurality of bits (col. 8, lines 65-col. 9, lines 2).
With respect to claim 13, Maltabas et al. discloses the method of claim 7, wherein activating the time-to-voltage converter circuit at a plurality of time points includes waiting a random time period between a first activation of the time-to-voltage converter circuit and a second activation of the time-to-voltage converter circuit (col. 11, lines 3-10).
With respect to claim 14, Maltabas et al. discloses an apparatus, comprising: a clock generation circuit configured to generate a clock signal (col. 15, lines 30-40); a plurality of circuit blocks configured to receive the clock signal (col. 4, lines 8-17); and
a jitter sensor circuit (col. 2, lines 40-48) configured to:
generate a reference voltage using a power supply voltage (col. 3, lines 21-31);
generate, at random time points, a sample signal using the reference voltage, wherein a first voltage level of the sample signal is proportional to a period of time the clock signal is at a particular logic value (col. 3, lines 42-55); and
generate an output signal based on the sample signal, wherein the output signal includes a plurality of bits whose value is indicative of the period of time the clock signal is the particular logic value (col. 5, lines 49-55).
With respect to claim 16, Maltabas et al. discloses the apparatus of claim 14, wherein the jitter sensor circuit is further configured to offset the sample signal using the reference voltage (col. 2, lines 40-48).
With respect to claim 17, Maltabas et al. discloses the apparatus of claim 14, wherein to generate the output signal, the jitter sensor circuit is further configured to:
convert the output signal to a feedback voltage using the reference voltage (col. 2, lines 40-48); perform a comparison of the feedback voltage to the sample signal; and adjust the output signal using a result of the comparison (col. 10, lines 61-67).
With respect to claim 18, Maltabas et al. discloses the apparatus of claim 17, wherein the jitter sensor circuit includes an analog-to-digital converter circuit (col. 11, lines 30-38) and a plurality of capacitors whose respective first terminals are coupled to an input node of the analog-to-digital converter circuit (col. 11, lines 30-38), and wherein to convert the output signal to the feedback voltage, the jitter sensor circuit is further configured to couple respective second
terminals of the plurality of capacitors to the reference voltage based on values of corresponding bits of the plurality of bits (col. 5, lines 49-55).
With respect to claim 20, Maltabas et al. discloses the apparatus of claim 14, wherein the jitter sensor circuit includes a plurality of resistors, and wherein to generate the reference voltage (col. 2, lines 40-48), the jitter sensor circuit is further configured to:
generate a current from the power supply voltage to a ground supply node using the plurality of resistors; and generate the reference voltage using the current (delay adjustment signal 206 Fig. 2; this adjusts a power supply voltage).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARHANA AKHTER HOQUE whose telephone number is (571)270-7543. The examiner can normally be reached Monday-Friday, 7:30am-4:00pm.
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/FARHANA A HOQUE/Primary Examiner, Art Unit 2858
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