DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 14-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uchida U.S. Patent Application Publication 2007/0300202 A1 (the ‘202 reference).
The reference discloses in Fig. 14 and related text an integrated circuit device as claimed.
Referring to claim 14, the reference discloses an integrated circuit (IC) device, comprising:
first and second circuits (comprising PMOS 11/NMOS 21 and PMOS 14/NMOS 24, para [51] (paragraph(s) [0051])) configured to perform corresponding functions (as inverters, para [6, 55]), wherein
the first circuit (11/21) comprises first and second active regions (p+ active region of transistor 11 and n+ active region of transistor 21, para [51]) extending along a first direction (horizontal direction) and spaced from each other along a second direction (vertical direction) transverse to the first direction,
the second circuit (14/24) comprises third and fourth active regions (p+ active region of transistor 14 and n+ active region of transistor 24, para [51]) extending along the first direction and spaced from each other along the second direction;
a first common conductive region (metal stud 81a and a portion of VDD rail 81 (~81a/81)) over and electrically coupled to a first common source region which is common to both the first active region and the third active region (para [55]: PMOS transistors 11 and 14 have a common source region, connected through a metal stub 81a to the vdd rail 81); and
a second common conductive region (metal stud 82a and a portion of ground rail 82 (~82a/82)) over and electrically coupled to a second common source region which is common to both the second active region and the fourth active region (para [55]: “NMOS transistors 21 and 24 have a common source region, connected through a metal stub 82a to the ground rail 8”).
Referring to claim 15, the reference further discloses that
the first active region (the p+ active region of transistor 11) further comprises a first source/drain region (drain region, para [55]) opposite to the first common source region along the first direction,
the second active region (n+ active region of transistor 21) further comprises a second source/drain region (drain region, para [55]) opposite to the second common source region along the first direction (the horizontal direction),
the third active region (p+ active region of transistor 14) further comprises a third source/drain region (drain region, para [55]) opposite to the first common source region along the first direction,
the fourth active region (n+ active region of transistor 24) further comprises a fourth source/drain region (drain region, para [55]) opposite to the second common source region along the first direction, and
at least one of the first to fourth active regions (the drain regions) is a drain region.
Referring to claim 16, the reference further discloses that
the first and second circuits (11/21 and 14/24) further comprise a plurality of gate regions (of transistors 11 and 21, of transistors 14 and 24, para[55]) extending along the second direction, adjacent gate regions (those of transistors 11 and 21, those of transistors 21 and 24) among the plurality of gate regions spaced from each other along the first direction (the horizontal direction) by one gate region pitch,
the IC device further comprises:
a third circuit (comprising PMOS 15/NMOS 25, para [51]) identical to the first circuit (11/21); and
a fourth circuit (comprising PMOS 13/NMOS 23) identical to the second circuit (14/24),
the first source/drain region (of transistor 15) of the third circuit (15/25) and the third source/drain region (of transistor 13) of the fourth circuit (13/23) are spaced from each other, along the first direction (the horizontal direction), by one gate region pitch, and
the second source/drain region (of transistor 25) of the third circuit (15/25) and the fourth source/drain region (of transistor 23) of the fourth circuit (13/23) are spaced from each other, along the first direction (the horizontal direction), by one gate region pitch.
Referring to claim 18, the reference further discloses that the first and second circuits (11/21 and 14/24) further comprise a plurality of gate regions (of transistors 11 and 21, of transistors 14 and 24, para[55]) extending along the second direction, adjacent gate regions (those of transistors 11 and 21, those of transistors 21 and 24) among the plurality of gate regions spaced from each other along the first direction (the horizontal direction) by one gate region pitch (CPP), and
at least one of the first circuit (11/21) or the second circuit (14/24) is
an inverter (para [6, 55]) having a width of (substantially equal to) 1 CPP along the first direction, [or
a NAND gate having a width of 2 CPPs along the first direction].
Referring to claim 19, the reference discloses an integrated circuit (IC) device, comprising:
first and second circuits (comprising PMOS 11/NMOS 21 and PMOS 14/NMOS 24, para [51]) configured to perform corresponding functions (as inverters, para [6, 55]), wherein
the first and second circuits correspondingly comprise first and second active regions (active region of transistor 11 and active region of transistor 14) extending along a first direction (horizontal direction),
the first and second circuits (11/21 and 14/24) further comprise a plurality of gate regions (of transistors 11 and 21, of transistors 14 and 24, para[55]) extending along a second direction (vertical direction) transverse to the first direction, adjacent gate regions (those of transistors 11 and 21, those of transistors 21 and 24) among the plurality of gate regions spaced from each other along the first direction (the horizontal direction) by one gate region pitch (CPP); and
a first common conductive region (metal stud 81a and a portion of VDD rail 81 (~81a/81)) over and electrically coupled to a first source/drain region common to both the first active region and the second active region (para [55]: PMOS transistors 11 and 14 have a common source region, connected through a metal stub 81a to the vdd rail 81),
wherein at least one of the first circuit or the second circuit (11/21 or 14/24) is
an inverter (para [6, 55]) having a width of (substantially equal to) 1 CPP along the first direction, [or
a NAND gate having a width of 2 CPPs along the first direction].
Referring to claim 20, the reference further discloses:
third (comprising PMOS 15/NMOS 25, para [51]) and fourth (comprising PMOS 13/NMOS 23) circuits configured to perform corresponding functions,
wherein
the third and fourth circuits correspondingly comprise third and fourth active regions (active region of transistor 15 and active region of transistor 13) extending along the first direction (the horizontal direction),
the third and fourth active regions correspondingly comprise third and fourth source/drain regions (of transistors 15 and 13, para [55]) spaced from each other along the first direction by 1 CPP, and
at least one of the third circuit (15/25) or the fourth circuit (13/23) is
an inverter (para [6, 55]) having a width of (substantially equal to) 1 CPP along the first direction, [or
a NAND gate having a width of 2 CPPs along the first direction, or
an AND-OR-Invert (AOI) logic having a width of 4 CPPs along the first direction].
3. Claims 14-15 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. U.S. Patent Application Publication 2019/0164952 A1 (the ‘952 reference).
The reference discloses in Figs. 2A, 2C and related text an integrated circuit device as claimed.
Referring to claim 14, the reference discloses an integrated circuit (IC) device, comprising:
first and second circuits (T2a/T1a and T2x/T1x, and note that in Fig. 2C, transistor T1x is mislabeled as T2x and vice versa, para [45]: “source region S1 and the drain region D1x of the active region FN1 together with the gate GT3 shown in FIG. 2C correspond to the transistor T1x shown in FIG. 2A. Correspondingly, the source region S2 and the drain region D2x of the active region FN2 together with the gate GT3 shown in FIG. 2C correspond to the transistor T2x”) configured to perform corresponding functions (T2a/T1a as ESD circuit, para [28], T2x/T1x as inverter, para [19]), wherein
the first circuit (T2a/T1a) comprises first and second active regions (FN2 active region (para [38]) of transistor T2a and FN1 active region of transistor T1a) extending along a first direction (horizontal direction) and spaced from each other along a second direction (vertical direction) transverse to the first direction,
the second circuit (T2x/T1x) comprises third and fourth active regions (FN2 active region of transistor T2x and FN1 active region of transistor T1x) extending along the first direction and spaced from each other along the second direction;
a first common conductive region (ML2) over and electrically coupled to a first common source region (S2) which is common to both the first active region and the third active region (para [43]: “metal line ML2 is utilized to couple the source region S2”, para [45]: “transistors T2a and T2x share the source region S2 used as a common source region” ); and
a second common conductive region (ML1) over and electrically coupled to a second common source region (S1) which is common to both the second active region and the fourth active region (para [43]: “metal line ML1 is utilized to couple the source region S1”, para [45]: “transistors T1a and T1x share the source region S1 used as a common source region”).
Referring to claim 15, the reference further discloses that
the first active region (FN2 active region (para [38]) of transistor T2a) further comprises a first source/drain region (drain region D2, para [33]) opposite to the first common source region (S2) along the first direction,
the second active region (FN1 active region of transistor T1a) further comprises a second source/drain region (drain region D1, para [32]) opposite to the second common source region (S1) along the first direction (the horizontal direction),
the third active region (FN2 active region of transistor T2x) further comprises a third source/drain region (drain region D2x, para [45]) opposite to the first common source region (S2) along the first direction,
the fourth active region (FN1 active region of transistor T1x) further comprises a fourth source/drain region (drain region D1x, para [45]) opposite to the second common source region (S1) along the first direction, and
at least one of the first to fourth active regions (the drain regions) is a drain region.
Referring to claim 18, the reference further discloses that the first and second circuits (T2a/T1a and T2x/T1x) further comprise a plurality of gate regions (G2, G1 (para [32]), gate region of gate GT3 for transistor T2x and gate region of gate GT3 for transistor T1x, para [45]) extending along the second direction, adjacent gate regions (gate G2 and gate region of gate GT3 for transistor T2x, gate G1 and gate region of gate GT3 for transistor T1x) among the plurality of gate regions spaced from each other along the first direction (the horizontal direction) by one gate region pitch (CPP), and
at least one of the first circuit (T2a/T1a) or the second circuit (T2x/T1x) is
an inverter (para [19]) having a width of (substantially equal to) 1 CPP along the first direction, [or
a NAND gate having a width of 2 CPPs along the first direction].
Referring to claim 19 and using the same reference characters, interpretations, and citations as detailed above for claims 14 and 18 where applicable, the reference discloses an integrated circuit (IC) device, comprising:
first and second circuits (T2a/T1a and T2x/T1x, para [51]) configured to perform corresponding functions, wherein
the first and second circuits correspondingly comprise first and second active regions (active region of transistor T2a and active region of transistor T2x) extending along a first direction (horizontal direction),
the first and second circuits (T2a/T1a and T2x/T1x) further comprise a plurality of gate regions (gate G2, gate region of gate GT3 for transistor T2x, gate G1, and gate region of gate GT3 for transistor T1x) extending along a second direction (vertical direction) transverse to the first direction, adjacent gate regions (gate G2 and gate region of gate GT3 for transistor T2x, gate G1 and gate region of gate GT3 for transistor T1x) among the plurality of gate regions spaced from each other along the first direction (the horizontal direction) by one gate region pitch (CPP); and
a first common conductive region (ML2) over and electrically coupled to a first source/drain region (S2) common to both the first active region (active region of transistor T2a) and the second active region (active region of transistor T2x),
wherein [at least one of the first circuit or] the second circuit (T2a/T1a) is
an inverter (para [19]) having a width of (substantially equal to) 1 CPP along the first direction, [or
a NAND gate having a width of 2 CPPs along the first direction].
Allowable Subject Matter
4. Claims 1-13 are allowable over the prior art of record.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious an integrated circuit (IC) device with all exclusive limitations as recited in claims 1 and 17, which may be characterized (claim 1) in that the plurality of gate regions comprises a dummy gate region between the first source/drain region and the second source/drain region, and in that the third active region and the fourth active region share a common source region, and (claim 17) in that a dummy gate region is between at least one of: the first source/drain region of the third circuit and the third source/drain region of the fourth circuit, or the second source/drain region of the third circuit and the fourth source/drain region of the fourth circuit.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
08-29-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
Prosecution Insights