DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/26/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claim 8 objected to because of the following informalities:
Claim 8 recites “wherein position” in line 2. This requires an article adjective, the examiner suggests “wherein a position”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 11 through 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation "the first power supply lines" in line 2. There is insufficient antecedent basis for this limitation in the claim. The precedent in claim 1 was “a first power supply line”.
Claim 11 recites the limitation "the power supply switch circuit" in line 9. There is insufficient antecedent basis for this limitation in the claim. The precedent in claim 1 recites “a power switch circuit”.
Claim 12 depends from and incorporates claim 11.
Claim 13 recites the limitation "the power supply switch circuit" in line 2. There is insufficient antecedent basis for this limitation in the claim. The precedent in claim 1 recites “a power switch circuit”.
Claims 14 through 19 depend from and incorporate claim 13.
Claim 18 recites the limitation "the power supply switch circuit" in line 2. There is insufficient antecedent basis for this limitation in the claim. The precedent in claim 1 recites “a power switch circuit”.
Claim 16 recites “a fourth via” in line 3 and “an eighth power supply line 5. However, the claim does not comprise “a third via” or “a seventh power supply line” nor does any of its parent claims. It is therefore unclear and ambiguous how many vias or power supply lines are present. The examiner suggests making the claim depend from a claim that does comprise “a third via” and “a seventh power supply line” in order to provide clarity and avoid ambiguity.
Claim 17 recites “a ninth power supply line” in line 3 and “a fifth via” in line 7.
However, the claim does not comprise “a fourth via” or “an eighth power supply line” nor does any of its parent claims. It is therefore unclear and ambiguous how many vias or power supply lines are present. The examiner suggests making the claim depend from a claim that does comprise “a fourth via” and “a eighth power supply line” in order to provide clarity and avoid ambiguity.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 4, 5, 6, 13, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 2017/0154655) in view of Beyne (US 2018/0145030)
Regarding claim 1.
Seo teaches:
A semiconductor device comprising: a substrate (fig 11:100; [para 0173]) that includes a first surface and a second surface opposite to the first surface (fig 11 annotated);
a first power supply line (fig 11:M1-1; [para 0125]) and a second power supply line (fig 11:M2-1; [para 0125]) arranged on the first surface;
a power switch circuit (fig 11:140; [para 0179]) arranged on the first surface and electrically connected between the first power supply line (fig 11:M1-1; [para 0125]) and the second power supply line (fig 11:M2-1; [para 0125]);
a third power supply line and a fourth power supply line arranged on the second surface;
a first via (fig 11:TSV2; [para 0175]) formed in the substrate (fig 11:100; [para 0173]) and connected to the first power supply line (fig 11:M1-1; [para 0125]) ;
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Seo does not teach that the device has vias connecting front side power lines to back side power lines.
Beyne teaches:
a first via (fig 7:16; [para 0058]) formed in the substrate (fig 4d,7:6; [para 0053]) and connected to the first power supply line (fig 7:8; [para 0058]) and the third power supply line (fig 7:60; [para 0058]);
and a second via (fig 7:17; [para 0058]) formed in the substrate (fig 4d,7:6; [para 0053]) and connected to the second power supply line (fig 7:9; [para 0058]) and the fourth power supply line (fig 7:61; [para 0058]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first via connecting first and third power lines and a second via connecting second and fourth power lines in order to transfer power from the backside of the substrate to the frontside where power can be supplied to devices.
Regarding claim 2.
Seo in view of Beyne teaches the semiconductor device according to claim 1,
wherein the first power supply line (fig 11:M1-1; [para 0125])and the second power supply line (fig 11:M2-1; [para 0125])are formed in the substrate (fig 11:100; [para 0173]).
Regarding claim 3.
Seo in view of Beyne teaches the semiconductor device according to claim 1,
the first power supply line (fig 11:M1-1; [para 0125]) and the second power supply line (fig 11:M2-1; [para 0125]) are formed in a wiring layer (fig 7:PL1,2; [para 0125]) arranged on or above the first surface (fig 7).
Regarding claim 4.
Seo in view of Beyne teaches the semiconductor device according to claim 1,
Beyne teaches:
a fifth power supply line (fig 7:9; [para 0058]) arranged on the first surface;
a third via (fig 7:16; [para 0058]) formed in the substrate (fig 4d,7:6; [para 0053]) and connected to the fifth power supply line (fig 7:9; [para 0058]);
a sixth power supply line (fig 7:61; [para 0058]) arranged on the second surface (fig 4d,7:6; [para 0053]) and connected to the third via (fig 7:16; [para 0058]).
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Regarding claim 5.
Seo in view of Beyne teaches the semiconductor device according to claim 4,
Beyne teaches:
the fifth power supply line (fig 7:9; [para 0058])is formed in the substrate (fig 4d,7:6; [para 0053]).
Regarding claim 6.
Seo in view of Beyne teaches the semiconductor device according to claim 4,
Beyne teaches:
the fifth power supply line (fig 7:9; [para 0058])is formed in a wiring layer (fig 7:12; [para 0058])arranged on or above the first surface.
Regarding claim 13.
Seo in view of Beyne teaches the semiconductor device according to claim 1,
Seo teaches:
the power supply switch circuit (fig 11:140; [para 0179])includes a switch transistor ([para 0176]) electrically connected (fig 11) between the first power supply line (fig 11:M1-1; [para 0125]) and the second power supply line (fig 11:M2-1; [para 0125]).
Regarding claim 15.
Seo in view of Beyne teaches the semiconductor device according to claim 13,
Seo teaches:
in a plan view, the first power supply line (fig 11:M1-1; [para 0125]) extends in the switch transistor (fig 11:140; [para 0179]) from a portion overlapping with the first via (fig 11:TSV2; [para 0175]).
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Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Seo (US 2017/0154655) in view of Beyne (US 2018/0145030) as applied to claim 13 and further in view of Schaefer (US 2014/0185392)
Regarding claim 18.
Seo in view of Beyne teaches the semiconductor device according to claim 13,
Seo teaches:
the power supply switch circuit (fig 11:140; [para 0179]) includes a control circuit (fig 11:PCS1; [para 0176])configured to control the switch transistor (fig 11:140; [para 0179]),
Seo in view of Beyne does not teach the via is between the control circuit and the switch transistor.
Schaefer teaches:
the power supply switch circuit (fig 2:280; [para 0030])includes a control circuit (fig 2:270; [para 0030])configured to control the switch transistor (fig 2:280; [para 0030]), and the first via is located between the switch transistor (fig 2:280; [para 0030])and the control circuit (fig 2:270; [para 0030])in the plan view (fig 2).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the via to be between control circuitry and the power supply switch in order to efficiently arrange the layout of the devices.
Allowable Subject Matter
Claims 7, 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 8, 11, 12, 14, 16, 17, and 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, the prior art does not teach, in combination with other elements of the claim, a semiconductor device comprising: a substrate that includes a first surface and a second surface opposite to the first surface; a power switch circuit arranged on the first surface and electrically connected between the first power supply line and the second power supply line; a sixth power supply line arranged on the second surface and connected to the third via, the fifth power supply line includes a plurality of fifth power supply lines arranged in a first direction in a plan view, and the first power supply line is arranged between the fifth power supply lines in the first direction.
Regarding claim 11, the prior art does not teach, in combination with other elements of the claim, a semiconductor device comprising: a substrate that includes a first surface and a second surface opposite to the first surface; a power switch circuit arranged on the first surface and electrically connected between the first power supply line and the second power supply line; wherein the first power supply line includes a plurality of first power supply lines, the second power supply line includes a plurality of second power supply lines, the fifth power supply line includes a plurality of fifth power supply lines, the power supply switch circuit includes a plurality of power supply switch circuits, the plurality of first power supply lines are electrically connected to each other by the third power supply line, the plurality of second power supply lines are electrically connected to each other by the fourth power supply line, and the plurality of fifth power supply lines are electrically connected to each other by the sixth power supply line.
Regarding claim 14, the prior art does not teach, in combination with other elements of the claim, a semiconductor device comprising: a substrate that includes a first surface and a second surface opposite to the first surface; a power switch circuit arranged on the first surface and electrically connected between the first power supply line and the second power supply line; the switch transistor includes: a gate electrode; a plurality of source areas arranged on a side of the gate electrode; and a plurality of drain areas arranged on another side of the gate electrode, and further comprising: a plurality of first local conductive traces connected to the plurality of source areas; a plurality of second local conductive traces connected to the plurality of drain areas; a first conductive trace arranged on or above the plurality of first local conductive traces and connected to the plurality of first local conductive traces; and a second conductive trace arranged on or above the plurality of second local conductive traces and connected to the plurality of second local conductive traces.
Regarding claim 16, the prior art does not teach, in combination with other elements of the claim, a semiconductor device comprising: a substrate that includes a first surface and a second surface opposite to the first surface; a power switch circuit arranged on the first surface and electrically connected between the first power supply line and the second power supply line; a fourth via formed in the substrate and connected to the first power supply line, and an eighth power supply line arranged on the second surface and connected to the fourth via.
Regarding claim 17, the prior art does not teach, in combination with other elements of the claim, a semiconductor device comprising: a substrate that includes a first surface and a second surface opposite to the first surface; a power switch circuit arranged on the first surface and electrically connected between the first power supply line and the second power supply line; a ninth power supply line arranged on the first surface so that the switch transistor is interposed between the first power supply line and the ninth power supply line in a plan view; a fifth via formed in the substrate and connected to the ninth power supply line; and a tenth power supply line arranged on the second surface and connected to the fifth via.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/ANTONIO B CRITE/Primary Examiner, Art Unit 2817
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