DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 07/26/2024. Claims 1-20 are pending in the Application, of which Claims 1, 10 and 16 are independent.
Continuity/ Priority Information
The present Application 18785972 filed 07/26/2024 claims foreign priority to REPUBLIC OF KOREA, Application 10-2023-0133411, filed 10/06/2023.
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in REPUBLIC OF KOREA on10/06/2023. It is noted, however, that applicant has not filed a certified copy of the 10-2023-0133411 application as required by 37 CFR 1.55.
An attempt by the Office to electronically retrieve, under the priority document exchange program, the foreign application 10-2023-0133411 to which priority is claimed has FAILED on 03/06/2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/26/2024 and 11/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1as being anticipated by SHIH (Pub. No. US 20210320827) Pub. Date: 2021-10-14.
Regarding independent Claims 1, 10 and 16, SHIH discloses a method and an apparatus for adjusting equalization, comprising:
a host device; and a storage device configured to perform an eye open monitor (EOM) operation with respect to a signal received from the host device,
[0021] FIG. 1 illustrates a storage device 10, which includes a storage unit. The processing unit 150 may receive host commands from the host side, such as host read, write, and erase commands defined in the UFS specifications, through the PHY 110 and the MAC layer 130. [0027] The PHY 110 includes an eye-diagram analyzer 123 “eye open monitor (EOM)” and the processing unit 150 may issue a signal to the eye-diagram analyzer 123 to activate the eye-diagram analyzer 123.
store the EOM result value in a buffer memory, and configured to output the EOM result value to the host device in response to an asynchronous event request (AER) command from the host device.
[0027] The processing unit 150 may issue a control signal to the eye-diagram analyzer 123 to activate the eye-diagram analyzer 123 depending on certain circumstances. The eye-diagram analyzer 123 transmits the calculated magnitudes “EOM result value” to the processing unit 150 when detecting that the successive waveforms output from the equalizer 122 belong to the eye close state, so that the processing unit 150 can adjust the equalizer 122 accordingly. The eye-diagram analyzer 123 transmits a message to the processing unit 150 to inform the processing unit 150 that the signals currently output from the equalizer 122 are acceptable when detecting that the successive waveforms output from the equalizer 122 belong to the eye open state.
an equalizer configured to adjust a gain of a received signal to generate equalized serial bits; input the equalized serial bits into a main path, to obtain a first output; and into an EOM path to obtain a second output;
[0024] The equalizer 122 includes a register 1225 and the processing unit 150 adjusts the parameters of the equalizer 122 in operation by setting the value of the register 1225. Refer to FIG. 2. [0036] Step S540: Registers 1225 are set to adjust the parameters of the equalizer 122 by using algorithms known by those skilled in the art according to the magnitudes calculated by the eye-diagram analyzer 123.
generate an error count signal based on a count of an error between the first output and the second output, and generate a sampling count signal based on a count of a comparison between the first output and the second output;
[0044] If the output of the equalizer 122 cannot be adjusted to belong to the eye open state after a predetermined period of time has elapsed or all possible candidate-value combinations of the parameters have been tried (the “Yes” path of step S560), corresponding to “count of an error”, it means that the adjustment to the equalizer 122 has failed, and the loop is exited.
an eye diagram generation (EGU) unit configured to generate, based on the error count signal and the sampling count signal, an eye diagram; and an analog front end (AFE) controller configured to control the equalizer based on the EOM result value.
Step S560: It is determined whether the adjustment has failed. If so, the process proceeds to step S570, “count of an error”. [0039] Step S570: Another error-correction mechanism is activated. For example, the processing unit 150 may send a message to the host side through the PHY 110 to notify the host side of a symbol decoding error. [0040] Step S580: A control signal is issued to the MUX 129 to connect parallel outputs of the symbol decoder 128 to the parallel inputs of the MAC layer 130 to back to the default connection.
Regarding Claims 2-4, 12-14, 18, 19, SHIH discloses an equalizer configured to adjust a gain of the received signal to generate equalized serial bits; a clock (CDR) block configured to use the equalized serial bits to recover the received signal; and an analog front end (AFE) controller configured to generate an AFE control signal for controlling the equalizer based on the EOM result value. Refer to FIG. 1. [0024] The equalizer 122 includes a register 1225 and the processing unit 150 adjusts the parameters of the equalizer 122 in operation by setting the value of the register 1225. Refer to FIG. 2. For example, the equalizer 122 includes a first-order Continuous Time Linear Equalizer (CTLE) 210 and a 1-tap Decision Feedback Equalizer (DFE) 230.
Regarding Claims 5-7, 15, SHIH discloses an EOM block configured to generate an error count signal based on a count of an error between the first output and the second output. [0045] Steps S530 and S580 are executed to repeatedly output fillers to the MAC layer 130 for replacing data output from the symbol decoder 128 after a symbol decoding error is detected until an adjustment failure or the successive waveforms output from the equalizer 122 have belonged to the eye open state. In some situations, the MAC layer 130 may directly trigger an error-correction mechanism held by the host side without waiting for results of the equalization adjustment after receiving a symbol decoding error message. The aforementioned steps would prevent the symbol decoding error message from being transmitted to the MAC layer 130, and further prevent triggering of an error-correction mechanism held by the host side.
Regarding Claims 11, 17, SHIH discloses wherein the performing comprises storing the EOM result value in the buffer memory, and wherein the transmitting comprises transmitting the EOM result value stored in the buffer memory to the host device. [0027] The processing unit 150 may issue a control signal to the eye-diagram analyzer 123 to activate the eye-diagram analyzer 123 depending on certain circumstances. The eye-diagram analyzer 123 transmits the calculated magnitudes “EOM result value” to the processing unit 150 “buffer memory” when detecting that the successive waveforms output from the equalizer 122 belong to the eye close state, so that the processing unit 150 can adjust the equalizer 122 accordingly.
Regarding Claims 8, 9, 20, SHIH discloses a first deserializer configured to generate the first output by deserializing the data of the equalized serial bits. [0023] The PHY 110 includes a deserializer 124, which converts high-speed serial signals received through an equalizer 122 into low-speed parallel signals. Signals received from the transmitter of the host and flew to the receiver of the storage device 10 may also be referred to as host data.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-21 of U.S. Patent No. 11,699,469. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant Application are broader in scope than the Claims recited in the U.S. Patent No. 11,699,46, and thus anticipate the Claims of the instant Application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
TABLE A: Claims comparison
18785972 Instant Application Claims
(U.S. Patent No. 11,699,469) Claims
Independent Claim 1.
a host device; and
a storage device configured to, based on being powered-on, perform an eye open monitor (EOM) operation with respect to a signal received from the host device to generate an EOM result value,
configured to store the EOM result value in a buffer memory, and configured to output the EOM result value within the buffer memory to the host device in response to receiving an asynchronous event request (AER) command from the host device.
Independent Claim 1. transmitting, by the host device, a request command for performing an eye-opening monitor (EOM) operation to a memory device; transmitting, by the host device, at least one parameter for performing the EOM operation to the memory device;
transmitting, by the host device, pattern data for performing the EOM operation to the memory device; and
receiving, by the host device, a first response signal including a result of the EOM operation performed based on the at least one parameter and the pattern data from the memory device, wherein the EOM operation is performed based on a comparison between a main path signal, which corresponds to a signal received from the host device and restored at the memory device, and
an EOM path signal, which corresponds to a signal received from the host device and restored using an offset value at the memory device, and wherein the at least one parameter for performing the EOM operation includes a parameter that defines the offset value.
Claim 2. wherein the request command for performing the EOM operation includes a write buffer command.
Independent Claim 10. A method of operating a storage system, the method comprising:
performing, by a storage device based on being powered-on, an eye open monitor (EOM) operation with respect to a received signal, to generate an EOM result value;
receiving an asynchronous event request (AER) command from a host device; and transmitting the EOM result value to the host device.
Independent Claim 9. A method of operating a memory device, the method comprising:
receiving, by the memory device, a request command for performing an eye-opening monitor (EOM) operation from a host device;
receiving, by the memory device,
at least one parameter for performing the EOM operation from the host device; receiving, by the memory device, pattern data for performing the EOM operation from the host device; and
performing, by the memory device, the EOM operation based on the at least one parameter and the pattern data and transmitting a first response signal including a result of performing the EOM operation to the host device,
wherein the performing the EOM operation comprises performing the EOM operation based on a comparison between a main path signal, which corresponds to a signal received from the host device and restored at the memory device, and
an EOM path signal, which corresponds to a signal received from the host device and restored using an offset value at the memory device, and wherein the at least one parameter for performing the EOM operation includes a parameter that defines the offset value.
Independent Claim 16. A storage device, comprising:
an equalizer configured to adjust a gain of a received signal to generate equalized serial bits;
an eye open monitor (EOM) unit configured to:
input the equalized serial bits into a main path, to obtain a first output based on a reference condition, the reference condition including a reference clock and a reference voltage;
input the equalized serial bits into an EOM path while changing an offset clock and an offset voltage, to obtain a second output; and
generate an error count signal based on a count of an error between the first output and the second output, and generate a sampling count signal based on a count of a comparison between the first output and the second output;
an eye diagram generation (EGU) unit configured to generate, based on the error count signal and the sampling count signal, an eye diagram in which the received signal is divided into unit intervals and values of divided segments are superimposed with each other, and configured to generate an EOM result value comprising at least one of the error count signal or the eye diagram; and
an analog front end (AFE) controller configured to control the equalizer based on the EOM result value.
Independent Claim 17. A memory system comprising:
a host device including a host controller; and
a memory device including a device controller and an eye-opening monitor (EOM), wherein the host controller is configured to transmit a request command for performing an EOM operation to the memory device, transmit at least one parameter for performing the EOM operation to the memory device,
transmit pattern data for performing the EOM operation to the memory device, and receive a first response signal including a result of the EOM operation performed based on the at least one parameter and the pattern data from the memory device,
wherein the EOM operation is performed based on a comparison between a main path signal, which corresponds to a signal received from the host device and restored at the memory device, and an EOM path signal, which corresponds to a signal received from the host device and restored using an offset value at the memory device, and
wherein the at least one parameter for performing the EOM operation includes a parameter that defines the offset value.
Claims 6, 2-4. 8, 9, 13-15 18, 19, wherein the storage device comprises: an equalizer configured to adjust a gain of the received signal to generate equalized serial bits;
The Claims in (U.S. Patent No. 11,699,469) fail to recite an equalizer configured to adjust a gain of the received signal to generate equalized serial bits.
However, referring to U.S. Patent 11,699,469, FIGS. 2 to 4, a clock RCK may be recovered from a signal S, which is received from the host device 100 and passed through an equalizer EQ, using a clock recovery circuit CDR, and data of the signal S is extracted using the recovered clock RCK such that a main path signal MS is generated.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to add an equalizer in the Claims of 11,699,469 for the purpose of recovering a signal by balancing the signal gain using an equalizer.
Claims 5-7 an EOM block configured to generate an error count signal based on a count of an error between the first output and the second output and generate a sampling count signal based on a count of comparison between the first output and the second output; and an eye diagram generation unit (EGU) configured to generate an eye diagram showing signals according to a clock and a voltage, based on the error count signal and the sampling count signal, and wherein the EOM result value comprises at least one of the error count signal or the eye diagram.
Claims 6, 14, wherein the first response signal includes least one of information on whether the EOM operation has been successfully performed and an error count value obtained according to the EOM operation.
Claims 12, 20. Setting an offset value, the offset value comprising an offset clock and an offset voltage; inputting the received signal into an eye open monitor (EOM) path, to obtain a second output by using a predetermined offset value,
Claims 5, 13. wherein the at least one parameter includes at least one of a time offset value, a phase offset value, and a voltage offset value.
Claims 6, 14. wherein the first response signal includes least one of information on whether the EOM operation has been successfully performed and an error count value obtained according to the EOM operation.
Claims 11, 17. wherein the performing comprises storing the EOM result value in the buffer memory, and wherein the transmitting comprises transmitting the EOM result value stored in the buffer memory to the host device.
Claim 2. wherein the request command for performing the EOM operation includes a write buffer command.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
CHOI et al. (US 20160209462) see, SUMMARY, [0005] According to an aspect of an exemplary embodiment there is provided an integrated circuit including an internal circuit and an eye opening monitor (EOM) configured to measure an eye diagram of a predetermined point of the internal circuit.
Kang et al. (U.S. Patent No. 11,699,469) See, Abstract, The operating method of a host device includes transmitting a request command for performing an eye-opening monitor (EOM) operation to a memory device, transmitting a parameter for performing the EOM operation to the memory device, transmitting pattern data for performing the EOM operation to the memory device, and receiving a first response signal including a result of the EOM operation performed based on the parameter and the pattern data from the memory device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: February 10, 2026
Non-Final Rejection 20260204
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV