DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2, 4-6, 11-13, 16-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 20170345761 A1) hereinafter referred to as "Yu".
Regarding claim 2, Yu teaches a package structure, comprising: a first redistribution structure (Fig. 9G, element 170; ¶: [0023]); a first semiconductor die (Fig. 9G, element 130; ¶: [0020]) attached to the first redistribution structure; a second semiconductor die (Fig. 9G, element 120; ¶: [0017]) stacked over and electrically connected to the first semiconductor die; an insulating encapsulant (Fig. 9G, element 160; ¶: [0022]) laterally encapsulating the first semiconductor die and the second semiconductor die, the insulating encapsulant comprising a first encapsulation portion and a second encapsulation portion continuous with the first encapsulation portion (Fig. 9G, element 160; ¶: [0022]), the first encapsulation portion being disposed on the first semiconductor die and laterally encapsulating the second semiconductor die, and the second encapsulation portion laterally encapsulating the first encapsulation portion and the first semiconductor die; a second redistribution structure (Fig. 9G, element 270; ¶: [0047]) on the first semiconductor die, the second semiconductor die, and a first surface of the insulating encapsulant, wherein the first redistribution structure is electrically connected to the second semiconductor die (Fig. 9G element 120, 270; ¶: [0024, 0047]); and conductive through vias (Fig. 9G, element 152; ¶: [0034]) disposed aside the first semiconductor die, wherein the conductive through vias penetrate through the second encapsulation portion of the insulating encapsulant (Fig. 9G, element 160; ¶: [0037]), wherein the second redistribution structure is electrically connected to the first redistribution structure through the conductive through vias (Fig. 9G, element 170, 270; ¶: [0023]).
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Regarding claim 4, Yu teaches a third semiconductor die (Fig. 9G, element 110; ¶: [0017]) stacked over and electrically connected to the first semiconductor die, (Fig. 9G, element 130; ¶: [0020]) wherein the first encapsulation portion (Fig. 9G, element 160; ¶: [0022]) extends between the second semiconductor die and the third semiconductor die.
Regarding claim 11, Yu teaches a package structure, comprising: a bottom tier die (Fig. 9G, element 130; ¶: [0020]); a top tier die (Fig. 9G, element 120; ¶: [0017]) on the bottom tier die, wherein the top tier die comprises a substrate and a through substrate via (Fig. 6, element 153; ¶: [0020]) protruding from the substrate, wherein a lateral dimension of the bottom tier die is greater than a lateral dimension of the top tier die (Fig. 9G, element 130, 120; ¶: [0020]); an insulating encapsulant (Fig. 9G, element 160; ¶: [0022]) covering the bottom tier die and the top tier die; and a first redistribution structure (Fig. 9G, element 270; ¶: [0047]) disposed on the top tier die and a top surface of the insulating encapsulant, wherein the through substrate vias contacts a conductive feature of the first redistribution structure.
Regarding claim 12, Yu teaches the insulating encapsulant (Fig. 9G, element 160; ¶: [0022]) extends between the top tier die and the first redistribution structure (Fig. 9G, element 270; ¶: [0047]).
Regarding claim 13, Yu teaches a through via (Fig. 9G, element 152; ¶: [0034]) extending through the insulating encapsulant.
Regarding claim 16, Yu teaches a package structure, comprising: a first redistribution structure (Fig. 9G, element 170; ¶: [0023]); a bottom tier die (Fig. 9G, element 130; ¶: [0020]) on the first redistribution structure; a top tier die (Fig. 9G, element 120; ¶: [0017]) on the bottom tier die, wherein the top tier die comprises a substrate and a through substrate via protruding from the substrate (Fig. 6, element 153; ¶: [0020]), wherein a lateral dimension of the bottom tier die is greater than a lateral dimension of the top tier die (Fig. 9G, element 130, 120; ¶: [0020]); an encapsulant (Fig. 9G, element 160; ¶: [0022]) on an upper surface of the bottom tier die and along sidewalls of the bottom tier die and the top tier die; and a second redistribution structure (Fig. 9G, element 270; ¶: [0047]) disposed over the top tier die and a top surface of the encapsulant, wherein the substrate is spaced apart from the second redistribution structure (Fig. 9G, element 270; ¶: [0048]), wherein the through substrate via contacts a conductive feature of the second redistribution structure.
Regarding claim 17, Yu teaches the encapsulant (Fig. 9G, element 160; ¶: [0022]) extends over an upper surface of the top tier die (Fig. 9G, element 120; ¶: [0017]).
Regarding claim 18, Yu teaches the encapsulant (Fig. 9G, element 160; ¶: [0022]) extends along sidewalls of the through substrate via.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20170345761 A1).
Regarding claim 5, Yu teaches the package structure of claim 2. In a different embodiment of the same invention, teaches the second semiconductor die (Fig. 6 element 120; ¶: [0024, 0047]) comprises a through substrate via (Fig. 6, element 153; ¶: [0020, 0056]), wherein the through substrate via contacts a conductive feature of the second redistribution structure (Fig. 6 element 170; ¶: [0056]).
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include substrate vias not only in the first, but also the second semiconductor die in order to perform flip chip bonding to the second redistribution structure (¶: [0056]).
Regarding claim 6, Yu teaches the first encapsulation portion (Fig. 6, element 160; ¶: [0037]) laterally encapsulates a portion of the through substrate via (Fig. 6, element 153; ¶: [0020]) and extends between the second semiconductor die (Fig. 6 element 120; ¶: [0024, 0047]) and the second redistribution structure (Fig. 6, element 170; ¶: [0023]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chen et al. (US 20210375826 A1) hereinafter referred to as "Chen 826".
Regarding claim 3, Yu does not teach the first semiconductor die being directly bonded to the second semiconductor die.
Chen 826 teaches the first semiconductor die being directly bonded to the second semiconductor die (Fig. 2B, element 100, 200; ¶: [0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to create a hybrid bonding interface and have both semiconductor dies be electrically connected (¶: [0035]).
Claims 7-10, 14-15, 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chen et al. (US 20200006309 A1) hereinafter referred to as "Chen 309".
Regarding claim 7, Yu teaches the package structure of claim 5. Yu does not teach a dielectric layer between the second semiconductor die and the second redistribution structure, the dielectric layer extending along sidewalls of the through substrate via.
Chen 309 teaches a dielectric layer (Fig. 3, element 54; ¶: [0031, 0032]) between the second semiconductor die and the second redistribution structure, the dielectric layer extending along sidewalls of the through substrate via.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a dielectric layer as an etch stop layer or a gap-filling isolation region (¶: [0031, 0034]).
Regarding claim 8, Yu in view of Chen 309 teaches the package structure of claim 7. Yu does not teach the dielectric layer extending along sidewalls of the second semiconductor die.
Chen 309 teaches the dielectric layer (Fig. 3, element 54; ¶: [0031, 0032) extending along sidewalls of the second semiconductor die.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a dielectric layer as an etch stop layer or a gap-filling isolation region (¶: [0031, 0034]).
Regarding claim 9, Yu in view of Chen 309 teaches the package structure of claim 8. Yu does not teach the dielectric layer extending along sidewalls of the first semiconductor die.
Chen 309 teaches the dielectric layer (Fig. 3, element 54; ¶: [0031, 0032) extending along sidewalls of the first semiconductor die.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a dielectric layer as an etch stop layer or a gap-filling isolation region (¶: [0031, 0034]).
Regarding claim 10, Yu in view of Chen 309 teaches the package structure of claim 9. Yu does not teach the dielectric layer separating the insulating encapsulant from the first redistribution structure.
Chen 309 teaches the dielectric layer (Fig. 3, element 54; ¶: [0031, 0032) separating the insulating encapsulant from the first redistribution structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a dielectric layer as an etch stop layer or a gap-filling isolation region (¶: [0031, 0034]).
Regarding claim 14, Yu teaches the package structure of claim 13. Yu does not teach a dielectric layer between the top tier die and the insulating encapsulant and between the top tier die and the first redistribution structure.
Chen 309 teaches a dielectric layer (Fig. 3, element 54; ¶: [0031, 0032) between the top tier die and the insulating encapsulant and between the top tier die and the first redistribution structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a dielectric layer as an etch stop layer or a gap-filling isolation region (¶: [0031, 0034]).
Regarding claim 15, Yu in view of Chen 309 teaches the package structure of claim 14. Yu does not teach the dielectric layer extending between the through via and the insulating encapsulant.
Chen 309 teaches the dielectric layer (Fig. 3, element 54; ¶: [0031, 0032) extending between the through via and the insulating encapsulant.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a dielectric layer as an etch stop layer or a gap-filling isolation region (¶: [0031, 0034]).
Regarding claim 19, Yu teaches the package structure of claim 16. Yu does not teach a dielectric layer covering the bottom tier die and the top tier die, wherein the through substrate via penetrates through a portion of the dielectric layer on a back surface of the top tier die.
Chen 309 teaches a dielectric layer (Fig. 3, element 54; ¶: [0031, 0032) covering the bottom tier die and the top tier die, wherein the through substrate via penetrates through a portion of the dielectric layer on a back surface of the top tier die.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a dielectric layer as an etch stop layer or a gap-filling isolation region (¶: [0031, 0034]).
Regarding claim 20, Yu in view of Chen 309 teaches the package structure of claim 19. Yu does not teach the second redistribution structure directly contacting an upper surface of the dielectric layer.
Chen 309 teaches the second redistribution structure directly contacting an upper surface of the dielectric layer (Fig. 3, element 54; ¶: [0031, 0032).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a dielectric layer as an etch stop layer or a gap-filling isolation region (¶: [0031, 0034]).
Regarding claim 21, Yu in view of Chen 309 teaches the package structure of claim 19. Yu does not teach a through via extending through the encapsulant from the first redistribution structure to the second redistribution structure, wherein the dielectric layer extends between the through via and the encapsulant.
Chen 309 teaches a through via extending through the encapsulant from the first redistribution structure to the second redistribution structure, wherein the dielectric layer (Fig. 3, element 54; ¶: [0031, 0032) extends between the through via and the encapsulant.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a dielectric layer as an etch stop layer or a gap-filling isolation region (¶: [0031, 0034]).
Conclusion
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/I.H./ Examiner, Art Unit 2899 /LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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