DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 07/26/2024.
Claims 1-20 are pending. Claims 1, 7, and 13 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Domestic Priority
4. See ADS for domestic priority details.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 07/26/2024. This IDS has been considered.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Interpretation (invoking 35 U.S.C. §112(f))
6. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are claims 1-20:
Claim 1. An apparatus, comprising:
a memory component including an array of memory cells, wherein the array includes a plurality of access lines to which the memory cells are coupled; and
a processing device coupled to the memory component and configured to perform a program operation on the array of memory cells, wherein the program operation includes:
programming data to be stored in one page of memory cells of the array to the memory cells of the array coupled to a first one of the plurality of access lines; (1)
programming additional data to be stored in the one page of memory cells of the array to the memory cells of the array coupled to a second one of the plurality of access lines, wherein the second one of the plurality of access lines is adjacent to the first one of the plurality of access lines; (2)
sensing the data programmed to the memory cells of the array coupled to the first one of the plurality of access lines; and (3)
programming data to be stored in two pages of memory cells of the array to the memory cells of the array coupled to the first one of the plurality of access lines. (4)
Claim 2. The apparatus of claim 1, wherein the program operation includes:
programming additional data to be stored in the one page of memory cells of the array to the memory cells of the array coupled to a third one of the plurality of access lines, wherein the third one of the plurality of access lines is adjacent to the second one of the plurality of access lines; (5)
sensing the additional data to be stored in the one page of memory cells of the array and programmed to the memory cells of the array coupled to second one of the plurality of access lines; and (6)
programming additional data to be stored in the two pages of memory cells of the array to the memory cells of the array coupled to the second one of the plurality of access lines. (7)
Claim 3. The apparatus of claim 1, wherein: the data and the additional data to be stored in the one page of memory cells of the array is single level cell (SLC) data; and
the data to be stored in the two pages of memory cells of the array is multi-level cell (MLC) data.
Claim 4. The apparatus of claim 1, wherein the processing device is configured to perform a sense operation on the array of memory cells, wherein the sense operation includes:
determining data stored in the one page of memory cells of the array using a first reference voltage; (8)
determining data stored in a first one of the two pages of memory cells of the array using a second reference voltage, a third reference voltage, and a fourth reference voltage; and (9)
determining data stored in a second one of the two pages of memory cells of the array using a fifth reference voltage, a sixth reference voltage, and a seventh reference voltage. (10)
Claim 5. The apparatus of claim 1, wherein the program operation includes:
loading the additional data to be stored in the one page of memory cells of the array after programming the data to be stored in the one page of memory cells of the array; (11)
loading the data to be stored in the two pages of memory cells of the array after programming the additional data to be stored in the one page of memory cells of the array; and (12)
sensing the data programmed to the memory cells of the array coupled to the first one of the plurality of access lines after loading the data to be stored in the two pages of memory cells of the array. (13)
Claim 6. The apparatus of claim 1, wherein each respective one of the plurality of access lines corresponds to a different vertical level of the array.
Claim 7. A method of operating memory, comprising:
performing a program operation on an array of memory cells, wherein the program operation includes:
programming data to be stored in one page of memory cells of the array to memory cells of the array coupled to each of a plurality of adjacent access lines of the array; and (14)
programming data to be stored in two pages of memory cells of the array to the memory cells of the array coupled to each of the plurality of adjacent access lines of the array; (15)
wherein the data to be stored in the two pages of memory cells of the array is programmed after the data to be stored in the one page of memory cells of the array is programmed; and
performing a sense operation on the array of memory cells, wherein the sense operation includes:
determining data stored in the one page of memory cells of the array using a first reference voltage; (16)
determining data stored in a first one of the two pages of memory cells of the array using a second reference voltage, a third reference voltage, and a fourth reference voltage; and (17)
determining data stored in a second one of the two pages of memory cells of the array using a fifth reference voltage, a sixth reference voltage, and a seventh reference voltage. (18)
Claim 8. The method of claim 7, wherein the plurality of adjacent access lines comprises a portion of the access lines of the array.
Claim 9. The method of claim 8, wherein the method includes performing an additional program operation on the array of memory cells, wherein the additional program operation includes programming additional data to be stored in additional pages of memory cells of the array to memory cells of the array coupled to the access lines of the array not included in the portion of the adjacent access lines. (19)
Claim 10. The method of claim 7, wherein an error rate associated with the plurality of adjacent access lines of the array meets or exceeds a particular error rate threshold.
Claim 11. The method of claim 7, wherein a temperature of the plurality of adjacent access lines of the array is within a particular temperature range.
Claim 12. The method of claim 7, wherein the program operation includes loading the data to be stored in the two pages of memory cells of the array after programming the data to be stored in the one page of memory cells of the array. (20)
Claim 13. An apparatus, comprising:
a memory component including an array of memory cells, wherein the array includes a plurality of access lines to which the memory cells are coupled; and
a processing device coupled to the memory component and configured to:
select a portion of the plurality of access lines of the array for a program operation; and (21)
perform the program operation, wherein the program operation includes:
programming data to be stored in one page of memory cells of the array to the memory cells of the array coupled to a first one of the plurality of access lines included in the selected portion; (22)
programming additional data to be stored in the one page of memory cells of the array to the memory cells of the array coupled to a second one of the plurality of access lines included in the selected portion, wherein the second one of the plurality of access lines is adjacent to the first one of the plurality of access lines in the selected portion; (23)
sensing the data programmed to the memory cells of the array coupled to the first one of the plurality of access lines included in the selected portion; and (24)
programming data to be stored in two pages of memory cells of the array to the memory cells of the array coupled to the first one of the plurality of access lines included in the selected portion. (25)
Claim 14. The apparatus of claim 13, wherein the processing device is configured to: select an additional portion of the plurality of access lines of the array for an additional program operation; and (26)
perform the additional program operation. (27)
Claim 15. The apparatus of claim 14, wherein the additional program operation includes:
programming data to be stored in an additional one page of memory cells of the array to the memory cells of the array coupled to a first one of the plurality of access lines included in the selected additional portion; (28)
programming additional data to be stored in the additional one page of memory cells of the array to the memory cells of the array coupled to a second one of the plurality of access lines included in the selected additional portion, wherein the second one of the plurality of access lines is adjacent to the first one of the plurality of access lines in the selected additional portion; (29)
sensing the data programmed to the memory cells of the array coupled to the first one of the plurality of access lines included in the selected additional portion; and (30)
programming data to be stored in an additional two pages of memory cells of the array to the memory cells of the array coupled to the first one of the plurality of access lines included in the additional selected portion. (31)
Claim 16. The apparatus of claim 14, wherein the additional program operation includes:
programming data to be stored in an additional one page of memory cells of the array to the memory cells of the array coupled to each of the plurality of access lines included in the selected additional portion; and (32)
programming data to be stored in an additional two pages of memory cells of the array to the memory cells of the array coupled to each of the plurality of access lines included in the selected additional portion; (33)
wherein the data to be stored in the additional two pages of memory cells of the array is programmed after the data to be stored in the additional one page of memory cells of the array is programmed.
Claim 17. The apparatus of claim 14, wherein:
the portion of the plurality of access lines of the array are included in a first deck of the array; and
the additional portion of the plurality of access lines of the array are included in a second deck of the array.
Claim 18. The apparatus of claim 13, wherein the processing device is configured to perform an additional program operation on the selected portion, wherein the additional program operation includes:
programming data to be stored in the one page of memory cells of the array to the memory cells of the array coupled to each of the plurality of access lines included in the selected portion; and (34)
programming data to be stored in the two pages of memory cells of the array to the memory cells of the array coupled to each of the plurality of access lines included in the selected portion. (35)
Claim 19. The apparatus of claim 13, wherein the processing device is configured to select the portion of the plurality of access lines of the array for the program operation based on an error rate associated with the portion of the plurality of access lines. (36)
Claim 20. The apparatus of claim 13, wherein the processing device is configured to select the portion of the plurality of access lines of the array for the program operation based on a temperature of the portion of the plurality of access lines. (37)
The term (s) "…apparatus…memory component…processing device…" in each of the limitations (1) - (13) and (21) – (37) above is a generic placeholder that is not preceded by a structural modifier. For instance, none of the modifiers of “memory component” and/ or “processing device" or a term with apparatus recites structure to perform the respective function(s). The term (s) "…performing program operation…" in each of the limitations (14) - (20) above is a generic placeholder that is not preceded by a structural modifier. For instance, none of the modifiers of “performing program operation” or a term with method recites structures or algorithm to perform the respective function(s).
Because the limitations above are being interpreted under 35 U.S.C. 112(f), they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. However, the specification does not appear to set forth corresponding structure(s) for the recited functions in the
limitations (1) through (37) above.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112(a)
7. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. — The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
8. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Independent claims 1, 7, and 13 fail to comply with the written description requirement, because the claims recite functional limitations e.g., programming, sensing, selecting, determining (1) - (4), (14) - (18) and (21) – (25) above (see Claim Construction Section in this Office action) without having adequate support for corresponding structure(s) in the specification as these claim limitations invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (see Claim Interpretation above as set forth in this Office action). As such, claim 1, 7, 13 recite functions that have no limits and covers every conceivable means for achieving the stated function in each of the limitations (1) - (4), (14) - (18) and (21) - (25) above. That is, the Applicant fails to provide corresponding structure or acts that one of ordinary skill in the art would be able to determine its structural or functional equivalence. Without being able to determine this, how would one of ordinary skill in the art have the requisite notice that to infringe on the claim. There is no/ none diagrams, figures, algorithms that shows or, correlates with the functional limitations and functional characteristics. Disclosure para [0024]-para [0026] describes the claimed functional features using black box type approach which can be software, hardware, or a combination of hardware/ software. Fig. 1 disclosure teaches circuitry but it is not clearly described how Fig. 1 circuitry components relate to the functions being claimed. Processing device described in para [0019] is very general, vague and does not correlate to the functional limitations being described. Limitations (1) - (4), (14) - (18) and (21) - (25) above are directed to selective programming pages for MLC, SLC using upper, lower, middle page programming scheme which requires specific hardware for selective programming. All limitations directed to specific enabling and triggering feature require specific hardware circuitry. Spec fails to show and describe any specific hardware associated with limitations (1) - (4), (14) - (18) and (21) - (25) above. Also, spec fails to disclose specific algorithm needed for the method claims. Therefore, each of these limitations invokes the scrutiny of interpretation under 35 U.S.C. 112(f) and requires that the Applicant affirmatively disclaim that the Applicant wishes to be limited to particular corresponding structure(s) in the written description or amend the claim to falls outside of scrutiny of interpretation under 35 U.S.C. 112(f). Accordingly, the disclosure is not commensurate with the scope of the claims.
Similarly, remaining claims (see above) fail to comply with the written description requirement, because the claim recites functional limitations (5) - (13), (19) - (21) and (26) - (37) above (see Claim Construction Section in this Office action) without having adequate support for corresponding structure(s) in the specification.
All dependent claims inclusive of claims 1-20 are rejected under this same category. See art rejection for the interpretation of the associated claims.
Claim Rejections - 35 USC § 112(b)
9. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
10. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant(s) regard as their invention.
Here, the independent claim 1, 7, 13 are indefinite, because it is unclear what
corresponding structure(s)are used for performing the entire claimed function in the limitations (1) - (4), (14) - (18) and (21) – (25) above (see Claim Interpretation section above) and the written description fails to clearly disclose or link the corresponding structure to the entire claimed function. Each of limitations (1) - (4), (14) - (18) and (21) – (25) above invokes the scrutiny of interpretation under 35 U.S.C. 112(f) and requires that the Applicant affirmatively disclaim that the Applicant wishes to be limited to particular corresponding structure(s) in the written description or amend the claim to falls outside of scrutiny of interpretation under 35 U.S.C. 112(f). Therefore, these claims are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Similarly, remaining claims (see above) fail to comply with the definiteness requirement, because the claim recites functional limitations (5) - (13), (19) - (21) and (26) - (37) above (see Claim Construction Section in this Office action) without having adequate support for corresponding structure(s) in the specification.
All dependent claims inclusive of claims 1-20 are rejected under this same category. See art rejection for the interpretation of the associated claims.
The Applicant can amend:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
Or
The Applicant can affirmatively disclaim:
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01 (o) and 2181.
Claim Rejections - 35 USC § 102
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
12. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
13. Claims 7-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yang et al. (US 2024/0071509 A1).
Regarding independent claim 7, Yang teaches a method of operating memory (Fig. 13: steps of programming memory device), comprising:
performing a program operation on an array of memory cells (para [0117]-para [0118]: programming a “memory block”),
wherein the program operation includes:
programming data to be stored in one page of memory cells of the array (SLC data. See also para [0118]: “SLC format” data) to memory cells of the coupled to each of a plurality of adjacent access lines of the array (Fig. 13: 1302-1304N: WL0-WLn is programmed with “SLC format” data. See para [0117]-para [0118]); and
programming data to be stored in two pages of memory cells of the array (MLC data. See also para [0118]: “MLC format” data) to the memory cells of the array coupled to each of the plurality of adjacent access lines of the array (Fig. 13: 1306-1308N: WL0-WLn is programmed with “MLC format” data. See para [0117]-para [0118]);
wherein the data to be stored in the two pages of memory cells of the array is programmed after the data to be stored in the one page of memory cells of the array is programmed (See Fig. 13 programming sequence and para [0118]); and
performing a sense operation on the array of memory cells (“read operation” and write “verify” operation),
wherein the sense operation includes:
determining data stored in the one page of memory cells of the array (Fig. 13: SLC data in WL0) using a first reference voltage (para [0119], lines 3-6: “read operation” of SLC from WL0 which requires Fig. 14B voltage level to distinguish 0, 1);
determining data stored in a first one of the two pages of memory cells of the array (Fig. 13: MLC data in WL0) using a second reference voltage, a third reference voltage, and a fourth reference voltage (Fig. 14D in context of para [0120], para [0121]: Verify voltages Vv1, Vv2, Vv3); and
determining data stored in a second one of the two pages of memory cells of the array (Fig. 13: MLC data in WL1) using a fifth reference voltage, a sixth reference voltage, and a seventh reference voltage (Fig. 14D in context of para [0123], para [0120], para [0121]: similar three verify voltages).
Regarding claim 8, Yang teaches the method of claim 7, wherein the plurality of adjacent access lines comprises a portion of the access lines of the array (interpreted as word lines in a selected block vs. all the word lines)
Claim Rejections - 35 USC § 103
14. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
15. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
16. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
17. Claims 1, 3, 13, and 14 is/are rejected under 35 U.S.C. 103 as being obvious over Han (US 2008/0031041 A1), in view of Luo (US 10,446,237 B1).
Regarding independent claim 1, Han teaches an apparatus (Fig. 8: 820 “memory system”. See Fig. 1-Fig. 8 for illustrated circuitry and functions), comprising:
a memory component (Fig. 8: 800 “memory device”) including an array of memory cells (Fig. 8: 830 “memory array”), wherein the array includes a plurality of access lines to which the memory cells are coupled (para [0045]: word line and memory cells); and
a processing device (Fig. 8: 870 control circuitry) coupled to the memory component (Fig. 8: 800) and configured to perform a program operation on the array of memory cells (see para [0048], Abstract, Fig. 2-Fig. 7 functions and programming),
wherein the program operation includes:
programming data to be stored in one page of memory cells of the array (Fig. 4: 1-bit data (“0” or “1”), i.e. SLC data requires one page e.g., “SLC page” to program. See Para [0024], para [0040], Fig. 6) to the memory cells of the array coupled to a first one of the plurality of access lines (Fig. 4: “1-bit” with WL0 and using programming sequence 1. See also para [0037]);
programming additional data (claim does not further describe additional data and is treated as SLC 1-bit data) to be stored in the one page of memory cells of the array (Fig. 4: 1-bit data (“0” or “1”), i.e. SLC data requires one page e.g., “SLC page” to program. See Para [0024], para [0040], Fig. 6) to the memory cells of the array coupled to a second one of the plurality of access lines (Fig. 4: “1-bit” with WL1 and using programming sequence 2. See also para [0037]),
wherein the second one of the plurality of access lines (Fig. 4: WL1) is adjacent to the first one of the plurality of access lines (Fig. 4: WL0);
sensing the data programmed to the memory cells of the array coupled to the first one of the plurality of access lines (para [0024], para [0026]: program verification operation is taught); and
programming data to be stored in two pages of memory cells of the array to the memory cells of the array (Fig. 4: 2-bit data, i.e. MLC data requires upper page and lower page to program. See Para [0037], para [0041], Fig. 7) coupled to the first one of the plurality of access lines (Fig. 4: “2-bit” with WL0 and using programming sequence 4/0. See also para [0037]).
Han teaches program verification after programming but is silent with respect to “sensing the data programmed to the memory cells of the array coupled to the first one of the plurality of access lines”.
Luo teaches -
sensing the data programmed to the memory cells of the array coupled to the first one of the plurality of access lines (Fig 5: 525 read results from “program pass” and verify against temperature compensated threshold voltage distribution. See col. 12, lines 52-64).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Luo’s temperature compensation teachings into the apparatus of Han such that said programming method can be employed in order to minimize read/ write errors (col. 4, lines 1-10, 32-40).
Regarding claim 3, Han and Luo teach the apparatus of claim 1. Han teaches wherein: the data and the additional data to be stored in the one page of memory cells of the array is single level cell (SLC) data; and the data to be stored in the two pages of memory cells of the array is multi-level cell (MLC) data (see para [0037], Fig. 4).
Regarding independent claim 13, Han teaches an apparatus (Fig. 8: 820 “memory system”. See Fig. 1-Fig. 8 for illustrated circuitry and functions), comprising:
a memory component (Fig. 8: 800 “memory device”) including an array of memory cells (Fig. 8: 830 “memory array”),
wherein the array includes a plurality of access lines to which the memory cells are coupled (para [0045]: word line and memory cells); and
a processing device (Fig. 8: 870 control circuitry) coupled to the memory component (Fig. 8: 800) and configured to:
select a portion of the plurality of access lines of the array for a program operation (Fig. 4 and para [0031]: “memory block”); and
perform the program operation (see para [0048], Abstract, Fig. 2-Fig. 7 functions and programming),
wherein the program operation (Fig. 4: SMLC program operation) includes:
programming data to be stored in one page of memory cells of the array (Fig. 4: 1-bit data (“0” or “1”), i.e. SLC data requires one page e.g., “SLC page” to program. See Para [0024], para [0040], Fig. 6) to the memory cells of the array coupled to a first one of the plurality of access lines included in the selected portion (Fig. 4: “1-bit” with WL0 and using programming sequence 1. See also para [0037]);
programming additional data (claim does not further describe additional data and is treated as SLC 1-bit data) to be stored in the one page of memory cells of the array to the memory cells of the array (Fig. 4: 1-bit data (“0” or “1”), i.e. SLC data requires one page e.g., “SLC page” to program. See Para [0024], para [0040], Fig. 6) coupled to a second one of the plurality of access lines included in the selected portion (Fig. 4: “1-bit” with WL1 and using programming sequence 2. See also para [0037]),
wherein the second one of the plurality of access lines (Fig. 4: WL1) is adjacent to the first one of the plurality of access lines (Fig. 4: WL0) in the selected portion (Fig. 4);
sensing the data programmed to the memory cells of the array coupled to the first one of the plurality of access lines included in the selected portion (para [0024], para [0026]: program verification operation is taught); and
programming data to be stored in two pages of memory cells of the array to the memory cells of the array (Fig. 4: 2-bit data, i.e. MLC data requires upper page and lower page to program. See Para [0037], para [0041], Fig. 7) coupled to the first one of the plurality of access lines included in the selected portion (Fig. 4: “2-bit” with WL0 and using programming sequence 4/0. See also para [0037].
Han teaches program verification after programming but is silent with respect to “sensing the data programmed to the memory cells of the array coupled to the first one of the plurality of access lines”.
Luo teaches -
sensing the data programmed to the memory cells of the array coupled to the first one of the plurality of access lines (Fig 5: 525 read results from “program pass” and verify against temperature compensated threshold voltage distribution. See col. 12, lines 52-64).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Luo’s temperature compensation teachings into the apparatus of Han such that said programming method can be employed in order to minimize read/ write errors (col. 4, lines 1-10, 32-40).
Regarding claim 14, Han and Luo teach the apparatus of claim 13. Han teaches wherein the processing device is configured to: select an additional portion of the plurality of access lines of the array for an additional program operation; and perform the additional program operation Fig. 4 and para [0031]: interpreted as programming additional “memory block” or segment).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Yang (US 10,650,896 B1): Fig. 1-Fig. 5 disclosure applicable for all claims.
Nose (US 2022/0208270 A1): Fig. 1-Fig. 23 disclosure applicable for all claims.
Chu (US 2022/0415418 A1): Fig. 1-Fig. 24 disclosure applicable for all claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825