DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 6 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: receiving an analog input signal at an input terminal; converting the analog input signal to a digital signal in a frequency domain by a Delta-Sigma ADC circuit that includes a voltage controlled oscillator (VCO); converting the digital signal in the frequency domain to an analog output signal by a digital-to-analog converter (DAC) circuit; extracting an error component of the analog output signal; converting the error component of the analog output signal to a digital error signal; and summing the digital signal in the frequency domain and the digital error signal to produce a digital output signal corresponding to the analog input signal.
Claim 2 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 7 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein converting the analog input signal to the first digital signal in the frequency domain includes applying the analog input signal to a voltage controlled oscillator (VCO).
Claim 3 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 2 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: applying a first gain factor to a negative of the error component by a transimpedance amplifier; and applying an inverse of the first gain factor to the digital error signal.
Claim 4 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 4 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: delaying the first digital signal before summing the first digital signal and the digital error signal.
Claim 6 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 6 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: amplifying (amplify function is part of converting error component) a negative of the error component.
Claim 7 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 6 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: filtering (filtering function is part of converting error component) before summing.
Claim 8 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 9 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: an input terminal configured to receive an analog input signal; a Delta-Sigma ADC circuit coupled to the input terminal, wherein the Delta- Sigma ADC is configured to convert the analog input signal to a digital signal in a frequency domain, and wherein the Delta-Sigma ADC circuit comprises a voltage controlled oscillator (VCO); a digital-to-analog converter (DAC) circuit connected to the Delta-Sigma ADC, wherein the DSC circuit is configured to convert the digital signal in the frequency domain to an analog output signal; a first summation circuit configured to extract an error component of the analog output signal; a first ADC circuit connected to the first summation circuit, wherein the second ADC circuit is configured to convert the error component of the analog output signal to a digital error signal; and a second summation circuit connected to the first ADC circuit, wherein the second summation circuit is configured to determine a sum of the digital signal in the frequency domain and the digital error signal to produce a digital output signal corresponding to the analog input signal.
Claim 9 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 9 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: first ADC circuit is a pipelined ADC.
Claim 10 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 10 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: a digital filter coupled to receive an output of the first ADC circuit, wherein the digital signal includes a noise transfer function, and wherein the digital filter comprises a digital filter function matching the noise transfer function to remove harmonic distortion from the digital signal.
Claim 11 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 12 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: a transimpedance amplifier connected to an output terminal of the summation block, and wherein the first ADC is connected to an output of the transimpedance amplifier.
Claim 12 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 12 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein the transimpedance amplifier is configured to apply a first gain factor to a negative of the error component, and wherein the ADC further comprises: a second amplifier coupled between the first ADC circuit and the second summation circuit, the second amplifier configured to apply an inverse of the first gain factor to the second digital signal.
Claim 13 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 13 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: a delay circuit coupled between the Delta-Sigma ADC circuit and the second summation circuit.
Claim 14 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 13 of U.S. Patent No.USP 11,438,007. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: the error component is filtered (filtering function is part of first ADC function) before summing.
Claim 1 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 17 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,143,126 discloses similar function and limitations as claimed in the claim of the instant application, such as: receiving an analog input signal at an input terminal; converting the analog input signal to a digital signal in a frequency domain by a Delta-Sigma ADC circuit that includes a voltage controlled oscillator (VCO); converting the digital signal in the frequency domain to an analog output signal by a digital-to-analog converter (DAC) circuit; extracting an error component of the analog output signal; converting the error component of the analog output signal to a digital error signal; and summing the digital signal in the frequency domain and the digital error signal to produce a digital output signal corresponding to the analog input signal.
Claim 2 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 17 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,143,126 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein converting the analog input signal to the first digital signal in the frequency domain includes applying the analog input signal to a voltage controlled oscillator (VCO).
Claim 3 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 17 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,143,126 discloses similar function and limitations as claimed in the claim of the instant application, such as: applying a first gain factor to a negative of the error component by a transimpedance amplifier; and applying an inverse of the first gain factor to the digital error signal.
Claim 4 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 19 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,143,126 discloses similar function and limitations as claimed in the claim of the instant application, such as: delaying the first digital signal before summing the first digital signal and the digital error signal.
Claim 5 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 20 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,143,126 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein converting the error component of the analog output signal to the digital error signal comprises converting the error component of the analog output signal to the digital error signal using a pipelined ADC.
Claim 6 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 17 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: amplifying (amplify function is part of converting error component) a negative of the error component.
Claim 7 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 17 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: filtering (filtering function is part of converting error component) before summing.
Claim 8 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 4 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,143,126 discloses similar function and limitations as claimed in the claim of the instant application, such as: an input terminal configured to receive an analog input signal; a Delta-Sigma ADC circuit coupled to the input terminal, wherein the Delta- Sigma ADC is configured to convert the analog input signal to a digital signal in a frequency domain, and wherein the Delta-Sigma ADC circuit comprises a voltage controlled oscillator (VCO); a digital-to-analog converter (DAC) circuit connected to the Delta-Sigma ADC, wherein the DSC circuit is configured to convert the digital signal in the frequency domain to an analog output signal; a first summation circuit configured to extract an error component of the analog output signal; a first ADC circuit connected to the first summation circuit, wherein the second ADC circuit is configured to convert the error component of the analog output signal to a digital error signal; and a second summation circuit connected to the first ADC circuit, wherein the second summation circuit is configured to determine a sum of the digital signal in the frequency domain and the digital error signal to produce a digital output signal corresponding to the analog input signal.
Claim 10 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 4 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,143,126 discloses similar function and limitations as claimed in the claim of the instant application, such as: a digital filter coupled to receive an output of the first ADC circuit, wherein the digital signal includes a noise transfer function, and wherein the digital filter comprises a digital filter function matching the noise transfer function to remove harmonic distortion from the digital signal.
Claim 11 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 4 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,143,126 discloses similar function and limitations as claimed in the claim of the instant application, such as: a transimpedance amplifier connected to an output terminal of the summation block, and wherein the first ADC is connected to an output of the transimpedance amplifier.
Claim 13 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 5 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 12,143,126 discloses similar function and limitations as claimed in the claim of the instant application, such as: a delay circuit coupled between the Delta-Sigma ADC circuit and the second summation circuit.
Claim 14 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 4 of U.S. Patent No.USP 12,143,126. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: filtering (filtering function is part of converting error component) before summing.
Claim 8 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 2 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: an input terminal configured to receive an analog input signal; a Delta-Sigma ADC circuit coupled to the input terminal, wherein the Delta- Sigma ADC is configured to convert the analog input signal to a digital signal in a frequency domain, and wherein the Delta-Sigma ADC circuit comprises a voltage controlled oscillator (VCO); a digital-to-analog converter (DAC) circuit connected to the Delta-Sigma ADC, wherein the DSC circuit is configured to convert the digital signal in the frequency domain to an analog output signal; a first summation circuit configured to extract an error component of the analog output signal; a first ADC circuit connected to the first summation circuit, wherein the second ADC circuit is configured to convert the error component of the analog output signal to a digital error signal; and a second summation circuit connected to the first ADC circuit, wherein the second summation circuit is configured to determine a sum of the digital signal in the frequency domain and the digital error signal to produce a digital output signal corresponding to the analog input signal.
Claim 9 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 3 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein the first ADC circuit is a pipelined ADC.
Claim 10 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 6 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: a digital filter coupled to receive an output of the first ADC circuit, wherein the digital signal includes a noise transfer function, and wherein the digital filter comprises a digital filter function matching the noise transfer function to remove harmonic distortion from the digital signal.
Claim 11 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 5 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: a transimpedance amplifier connected to an output terminal of the summation block, and wherein the first ADC is connected to an output of the transimpedance amplifier.
Claim 12 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 5 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: a second amplifier coupled between the first ADC circuit and the second summation circuit, the second amplifier configured to apply an inverse of the first gain factor to the second digital signal.
Claim 13 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 9 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: a delay circuit coupled between the Delta-Sigma ADC circuit and the second summation circuit.
Claim 14 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 2 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 11,438,007 discloses similar function and limitations as claimed in the claim of the instant application, such as: filtering (filtering function is part of converting error component) before summing.
Claim 15 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 1 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: an input terminal configured to receive an analog input signal; a first ADC circuit coupled to the input terminal, wherein the first ADC is configured to convert the analog input signal to a digital signal in a frequency domain, and wherein the first ADC circuit comprises a voltage controlled oscillator (VCO);a digital-to-analog converter (DAC) circuit connected to the first ADC, wherein the DAC circuit is configured to convert the digital signal in the frequency domain to an analog output signal; a loop filter (act as same first summation circuit) connected to the DAC circuit, wherein the loop filter is configured to extract an error component of the analog output signal; a second ADC circuit connected to the loop filter, wherein the second ADC circuit is configured to convert the error component of the analog output signal to a digital error signal; and a summation circuit connected to the second ADC circuit, wherein the summation circuit is configured to determine a sum of the digital signal in the frequency domain and the digital error signal to produce a digital output signal corresponding to the analog input signal.
Claim 16 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 3 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: wherein the second ADC circuit is a pipelined ADC.
Claim 17 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 6 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: a digital filter coupled to receive an output of the second ADC circuit, wherein the digital signal includes a noise transfer function, and wherein the digital filter comprises a digital filter function matching the noise transfer function to remove harmonic distortion from the digital signal.
Claim 18 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 5 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: a transimpedance amplifier connected to an output terminal of the first summation block, and wherein the second ADC is connected to an output of the transimpedance amplifier.
Claim 19 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 5 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: a second amplifier coupled between the second ADC circuit and the second summation circuit, the second amplifier configured to apply an inverse of the first gain factor to the second digital signal.
Claim 20 is rejected on the ground of non-statutory double patenting as being unpatentable over claim 9 of U.S. Patent No.USP 10,931,299. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim of USP 10,931,299 discloses similar function and limitations as claimed in the claim of the instant application, such as: a delay circuit coupled between the Delta-Sigma ADC circuit and the second summation circuit.
Conclusion
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/LAM T MAI/ Primary Examiner, Art Unit 2845