DETAILED ACTION
This non-final action is responsive to communications: application filed on 07/26/2024.
Claims 1-13 are pending. Claims 1 and 10 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 07/26/2024. This IDS has been considered.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
9. Claims 1-2, 5-6, and 8-11 is/are rejected under 35 U.S.C. 103 as being obvious over LEE-7718 (US 2012/0327718 A1), in view of LEE-7744 (US 2019/0057744 A1).
Regarding independent claim 1, LEE-7718 teaches a memory system (memory system employing Fig. 2 memory device. See Fig. 2-Fig. 9 for illustrated components and functionality) comprising:
a memory device (Fig. 2 “semiconductor memory device”) including a plurality of memory cells connected to each word line, among a plurality of word lines (see Fig. 3: WLs and C’s. See Fig. 2: 210); and
a memory controller (memory controller and Fig. 2: 220 combined) configured to generate a program command and control the memory device to perform a program operation (para [0032]- para [0033]: CMDi and program operation),
wherein the memory device comprises:
a peripheral circuit (Fig. 2: non-array circuitry shown) configured to perform the program operation (para [0033]-para [0034]) on selected memory cells that are connected to a selected word line (in context of Fig. 9: WLs-1 and associated cells), among the plurality of word lines, in response to receiving the program command (para [0032]-para [0034]); and
a control logic (Fig. 2: 220 control circuit) configured to control the peripheral circuit (Fig. 2: non-array circuitry) to:
perform an over-erasure cell sensing operation (Fig. 8 and Fig. 9 in context of para [0089]: operation performed on WLs and “…threshold voltages of over-erased memory cells having threshold voltages lower than the over-erase reference voltage Vpv0 of a negative potential…” are identified. See abstract: “…detecting over-erased memory cells having threshold voltages lower than an over-erase reference voltage…”) before performing a pre-program operation on over-erasure cells having a threshold voltage of an over-erasure state that is lower than a threshold voltage of an erasure state (Fig. 8, Fig. 9 in context of para [0089]: using LSB program loop identified over-erased cells in WLs “… are raised higher than the over-erase reference voltage Vpv0…”), and
perform the program operation on the selected memory cells (Fig. 8: 803 in context of para [0094]: “…MSB program loop is performed for memory cells coupled to a word line WLs-1 adjacent to the word line WLs…”) after performing the pre-program operation that increases a threshold voltage of the over-erasure cells, among adjacent memory cells that are connected to an adjacent word line, to the threshold voltage of the erasure state (Fig. 6A-Fig. 6Cpara [0089]-para [0091]: after performing over-erasure correction by raising threshold voltages of over-erased cells above vp0),
wherein the adjacent word line (Fig. 9, para [0089]: WLs. See Fig. 9) is a word line that is next to the selected word line (Fig. 9, para [0094]: WLs-1),
wherein the control logic determines memory cells that have threshold voltages that are lower than an over-erasure verify voltage (Fig. 6A, Fig. 6B, Fig. 6C: Vpv0 is over-erasure verify voltage), based on threshold voltages of the adjacent memory cells (based on WLs threshold voltages), as the over-erasure cells among the adjacent memory cells during the over-erasure cell sensing operation (Fig. 6A, Fig. 6B, Fig. 6C, Fig. 8, Abstract, para [0090]-para [0091]).
LEE-7718 is silent with respect to memory system architecture which employs the memory device.
LEE-7744 teaches a memory system (Fig. 1: memory system. See also para [0204]) comprising:
a memory device (Fig. 1: 100 “memory device”. See Fig. 2: 100) including a plurality of memory cells connected to each word line, among a plurality of word lines (para [0059]); and
a memory controller (Fig. 1: 200 memory controller) configured to generate a program command and control the memory device to perform a program operation (para [0039], para [0040]),
wherein the memory device comprises:
a peripheral circuit (Fig. 2: 120, 130) configured to perform the program operation (para [0041]) on selected memory cells that are connected to a selected word line, among the plurality of word lines, in response to receiving the program command (para [0039], para [0041], para [0042]); and
a control logic (Fig. 2: 130 control logic) configured to control the peripheral circuit (Fig. 2: 120, 130) to: perform an over-erasure cell sensing operation (para [0043]).
Both LEE-7718 and LEE-7744 are in the same field of endeavor of improving program operation of memory device and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine LEE-7744’s memory system architecture into the apparatus of LEE-7718 such that a computing system can be employed in order to improve reliability and operating method of memory device (LEE-7744 para [0209]).
Regarding claim 2, LEE-7718 and LEE-7744 teach the memory system of claim 1. LEE-7718 teaches wherein the adjacent memory cells are respectively connected to a plurality of bit lines (see Fig. 9: WLs adjacent word line cells are connected to plurality of bit lines),
wherein the control logic (Fig. 2: 220) is configured, in the pre-program operation, to control the peripheral circuit to apply a pre-program voltage to the adjacent word line (para [0089]: program loop is used on “over-erased memory cells” to raise threshold voltage “…higher than the over-erase reference voltage Vpv0…”),
apply a ground voltage to bit lines, among the plurality of bit lines, connected to the over-erasure cells (in context of para [0071]: “ground voltage” application scheme is disclosed and would be required for the embodiment of Fig. 8), and
apply a power voltage to bit lines, among the plurality of bit lines, connected to memory cells other than the over-erasure cells (para [0071]: “program inhibition voltage” application scheme is disclosed and would be required for the embodiment of Fig. 8), and
wherein the pre-program voltage is set to a level capable of increasing the threshold voltage of the memory cells having the threshold voltage of the over-erasure state to the threshold voltage of the erasure state (para [0071]: voltage e.g., “Vpgm” applied on over-erasure word line is disclosed and would be required for the embodiment of Fig. 8).
Regarding claim 5, LEE-7718 and LEE-7744 teach the memory system of claim 1. LEE-7718 teaches wherein the over-erasure verify voltage has the same voltage level as a lowest threshold voltage, among the threshold voltages of the erasure state (para [0089], Fig. 6A-Fig. 6C: Vpv0).
Regarding claim 6, LEE-7718 and LEE-7744 teach the memory system of claim 1. LEE-7718 teaches wherein the control logic is configured to control the peripheral circuit to
perform the program operation on memory cells that are connected to an m-th word line that is the selected word line after performing the pre-program operation on memory cells that are connected to an (m+1)-th word line, which is the adjacent word line (Fig. 8 in context of para [0089]-para [0094]: biasing scheme of word lines, adjacent word lines), and
to perform the program operation on memory cells that are connected to the (m+1)-th word line after performing the pre-program operation on memory cells that are connected to an (m+2)-th word line that is adjacent to the (m+1)-th word line (Fig. 8 in context of para [0089]-para [0094] where biasing scheme of WLs, WLs+1, WLs-1 can be applied in a repetitive manner to meet this functional limitation).
Regarding claim 8, LEE-7718 and LEE-7744 teach the memory system of claim 1. LEE-7718 teaches wherein the plurality of memory cells are included in a memory block (Fig. 2, Fig. 8 and para [0027], lines 1-9: memory cell block), and
wherein the control logic is configured to perform the program operation on the selected memory cells (Fig. 8, Fig. 9: WLs-1 and associated cells) after performing the pre-program operation on memory cells (Fig. 8, Fig. 9: “over-erased” cell identification and correction on WLs and associated cells), among the plurality of memory cells that are included in the memory block, connected to all word lines other than the selected word line.
Regarding claim 9, LEE-7718 and LEE-7744 teach the memory system of claim 1. LEE-7718 teaches wherein the plurality of memory cells includes memory cells that are programmed to any one state, among a plurality of program states (see Fig. 6A-Fig. 6C disclosure encompasses the limitation).
Regarding independent claim 10, LEE-7718 teaches a method of operating a memory system (Fig. 8 method of operating memory device of Fig. 2. See Fig. 2-Fig. 9 for illustrated components and functionality) comprising a memory device (Fig. 2 “semiconductor memory device”) including a plurality of memory cells connected to each word line, among a plurality of word lines (see Fig. 3: WLs and C’s. See Fig. 2: 210), and
a memory controller (memory controller and Fig. 2: 220 combined) controlling the memory device to perform a program operation on selected memory cells that are connected to selected word lines (in context of Fig. 9: WLs-1 and associated cells), among the plurality of word lines (para [0032]- para [0034]: CMDi and program operation), the method comprising:
sensing threshold voltages of adjacent memory cells that are connected to an adjacent word line, wherein the adjacent word line is a word line that is next to the selected word line (Fig. 8 and Fig. 9 in context of para [0089]: operation performed on WLs and “…threshold voltages of over-erased memory cells having threshold voltages lower than the over-erase reference voltage Vpv0 of a negative potential…” are identified. See abstract: “…detecting over-erased memory cells having threshold voltages lower than an over-erase reference voltage…”);
determining memory cells that have threshold voltages that are lower than an over-erasure verify voltage as over-erasure cells among the adjacent memory cells, wherein the over-erasure cells have a threshold voltage of an over-erasure state that is lower than a threshold voltage of an erasure state (Fig. 8 and Fig. 9 in context of para [0089]. See also Fig. 6A-Fig. 6C, para [0089]-para [0091]);
performing a pre-program operation that programs the over-erasure cells to the erasure state (Fig. 8, Fig. 9 in context of para [0089]: using LSB program loop identified over-erased cells in WLs “… are raised higher than the over-erase reference voltage Vpv0…”); and
performing the program operation on the selected memory cells (Fig. 8: 803 in context of para [0094]: “…MSB program loop is performed for memory cells coupled to a word line WLs-1 adjacent to the word line WLs…”).
LEE-7718 is silent with respect to memory system architecture which employs the memory device.
LEE-7744 teaches a memory system (Fig. 1: memory system. See also para [0204]) comprising:
a memory device (Fig. 1: 100 “memory device”. See Fig. 2: 100) including a plurality of memory cells connected to each word line, among a plurality of word lines (para [0059]); and
a memory controller (Fig. 1: 200 memory controller) configured to generate a program command and control the memory device to perform a program operation (para [0039], para [0040]),
wherein the memory device comprises:
a peripheral circuit (Fig. 2: 120, 130) configured to perform the program operation (para [0041]) on selected memory cells that are connected to a selected word line, among the plurality of word lines, in response to receiving the program command (para [0039], para [0041], para [0042]); and
a control logic (Fig. 2: 130 control logic) configured to control the peripheral circuit (Fig. 2: 120, 130) to: perform an over-erasure cell sensing operation (para [0043]).
Both LEE-7718 and LEE-7744 are in the same field of endeavor of improving program operation of memory device and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine LEE-7744’s memory system architecture and functions into the method/ apparatus of LEE-7718 such that a computing system can be employed in order to improve operational reliability (LEE-7744 para [0209]).
Regarding claim 11, LEE-7718 and LEE-7744 teach the method of claim 10. LEE-7718 teaches wherein the over-erasure verify voltage has the same voltage level as a lowest threshold voltage, among the threshold voltages of the erasure state (para [0089], Fig. 6A-Fig. 6C: Vpv0).
Double Patenting
10. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
11. Claims 1-13 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent US 12,087,376 B2, in view of LEE-7744 (US 2019/0057744 A1). Although the claims at issue are not identical, they are not patentably distinct from the claims of US 12,087,376 B2; see following analysis:
Regarding independent claim 1, US 12,087,376 B2 teaches a memory system (US 12,087,376 B2: apparatus configuration of claims 1-16 employed in a system) comprising:
a memory device including a plurality of memory cells connected to each word line, among a plurality of word lines (US 12,087,376 B2: claim 1, lines 1-3); and
a memory controller configured to generate a program command and control the memory device to perform a program operation,
wherein the memory device comprises: a peripheral circuit configured to perform the program operation on selected memory cells that are connected to a selected word line, among the plurality of word lines, in response to receiving the program command (US 12,087,376 B2: claim 1, lines 4-7); and
a control logic configured to control the peripheral circuit (US 12,087,376 B2: claim 1, lines 8-10) to:
perform an over-erasure cell sensing operation before performing a pre-program operation on over-erasure cells having a threshold voltage of an over-erasure state that is lower than a threshold voltage of an erasure state (US 12,087,376 B2: claim 1, lines 22-23), and
perform the program operation on the selected memory cells after performing the pre-program operation that increases a threshold voltage of the over-erasure cells, among adjacent memory cells that are connected to an adjacent word line, to the threshold voltage of the erasure state (US 12,087,376 B2: claim 1, lines 4-6, 8-16),
wherein the adjacent word line is a word line that is next to the selected word line (US 12,087,376 B2: claim 1, lines 16-18),
wherein the control logic determines memory cells that have threshold voltages that are lower than an over-erasure verify voltage, based on threshold voltages of the adjacent memory cells, as the over-erasure cells among the adjacent memory cells during the over-erasure cell sensing operation (US 12,087,376 B2: claim 1, lines 8-16).
US 12,087,376 B2 (claims 1-16) is silent with respect to memory system architecture which employs the memory device.
LEE-7744 teaches a memory system (Fig. 1: memory system. See also para [0204]) comprising:
a memory device (Fig. 1: 100 “memory device”. See Fig. 2: 100) including a plurality of memory cells connected to each word line, among a plurality of word lines (para [0059]); and
a memory controller (Fig. 1: 200 memory controller) configured to generate a program command and control the memory device to perform a program operation (para [0039], para [0040]),
wherein the memory device comprises:
a peripheral circuit (Fig. 2: 120, 130) configured to perform the program operation (para [0041]) on selected memory cells that are connected to a selected word line, among the plurality of word lines, in response to receiving the program command (para [0039], para [0041], para [0042]); and
a control logic (Fig. 2: 130 control logic) configured to control the peripheral circuit (Fig. 2: 120, 130) to: perform an over-erasure cell sensing operation (para [0043]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine LEE-7744’s memory system architecture into the apparatus of US 12,087,376 B2 (claims 1-16 apparatus configuration) such that a computing system can be employed in order to improve reliability and operating method of memory device (LEE-7744 para [0209]).
Regarding claim 2, US 12,087,376 B2 and LEE-7744 teach the memory system of claim 1. US 12,087,376 B2 wherein the adjacent memory cells are respectively connected to a plurality of bit lines, wherein the control logic is configured, in the pre-program operation, to control the peripheral circuit to apply a pre-program voltage to the adjacent word line (US 12,087,376 B2: claim 2, lines 1-3),
apply a ground voltage to bit lines, among the plurality of bit lines, connected to the over-erasure cells (US 12,087,376 B2: claim 2, lines 4-8), and
apply a power voltage to bit lines, among the plurality of bit lines, connected to memory cells other than the over-erasure cells (US 12,087,376 B2: claim 2, lines 9-11), and
wherein the pre-program voltage is set to a level capable of increasing the threshold voltage of the memory cells having the threshold voltage of the over-erasure state to the threshold voltage of the erasure state (US 12,087,376 B2: claim 2, lines 12-15).
Regarding claim 3, US 12,087,376 B2 and LEE-7744 teach the memory system of claim 1. US 12,087,376 B2 teaches wherein the pre-program operation includes a plurality of program loops, wherein each of the plurality of program loops includes a step of applying a pre-program voltage to the adjacent memory cells and a verify step of checking whether the adjacent memory cells are programmed to the erasure state, and wherein the pre-program voltage increases by a step voltage whenever a program loop increases (US 12,087,376 B2: claim 3, lines 1-9).
Regarding claim 4, US 12,087,376 B2 and LEE-7744 teach the memory system of claim 3. US 12,087,376 B2 teaches wherein the control logic is configured to control the peripheral circuit to perform the verify step by using the over-erasure verify voltage in the verify step, and wherein the over-erasure verify voltage has the same voltage level as a lowest threshold voltage, among the threshold voltages of the erasure state (US 12,087,376 B2: claim 4, lines 1-7).
Regarding claim 5, US 12,087,376 B2 and LEE-7744 teach the memory system of claim 1. US 12,087,376 B2 teaches wherein the over-erasure verify voltage has the same voltage level as a lowest threshold voltage, among the threshold voltages of the erasure state (US 12,087,376 B2: claim 5, lines 1-4).
Regarding claim 6, US 12,087,376 B2 and LEE-7744 teach the memory system of claim 1. US 12,087,376 B2 teaches wherein the control logic is configured to control the peripheral circuit to perform the program operation on memory cells that are connected to an m-th word line that is the selected word line after performing the pre-program operation on memory cells that are connected to an (m+1)-th word line, which is the adjacent word line, and (US 12,087,376 B2: claim 6, lines 1-11)
to perform the program operation on memory cells that are connected to the (m+1)-th word line after performing the pre-program operation on memory cells that are connected to an (m+2)-th word line that is adjacent to the (m+1)-th word line (US 12,087,376 B2: claim 6, lines 1-11).
Regarding claim 7, US 12,087,376 B2 and LEE-7744 teach the memory system of claim 1. US 12,087,376 B2 teaches wherein the control logic controls the peripheral circuit to perform the program operation on memory cells that are connected to an m-th word line which is the selected word line and an (m+1)-th word line which is the adjacent word line after performing the pre-program operation on memory cells that are connected to the (m+1)-th word line and an (m+2)-th word line that is adjacent to the (m+1)-th word line, and (US 12,087,376 B2: claim 7, lines 1-16)
perform the program operation on memory cells that are connected to the (m+2)-th word line and an (m+3)-th word line that is adjacent to the (m+2)-th word line after performing the pre-program operation on memory cells that are connected to the (m+3)-th word line and an (m+4)-th word line that is adjacent to the (m+3)-th word line, when the program operation on the memory cells that are connected to the (m+1)-th word line is completed. (US 12,087,376 B2: claim 7, lines 1-16)
Regarding claim 8, US 12,087,376 B2 and LEE-7744 teach the memory system of claim 1. US 12,087,376 B2 teaches wherein the plurality of memory cells are included in a memory block, and wherein the control logic is configured to perform the program operation on the selected memory cells after performing the pre-program operation on memory cells, among the plurality of memory cells that are included in the memory block, connected to all word lines other than the selected word line (US 12,087,376 B2: claim 8, lines 1-8).
Regarding claim 9, US 12,087,376 B2 and LEE-7744 teach the memory system of claim 1. US 12,087,376 B2 teaches wherein the plurality of memory cells includes memory cells that are programmed to any one state, among a plurality of program states (US 12,087,376 B2: claim 9, lines 1-3).
Similar analysis can be done for claims 10-13 to show NSDP rejection: (analysis not shown)
Claim 10. A method of operating a memory system comprising a memory device including a plurality of memory cells connected to each word line, among a plurality of word lines, and
a memory controller controlling the memory device to perform a program operation on selected memory cells that are connected to selected word lines, among the plurality of word lines, the method comprising:
sensing threshold voltages of adjacent memory cells that are connected to an adjacent word line, wherein the adjacent word line is a word line that is next to the selected word line;
determining memory cells that have threshold voltages that are lower than an over-erasure verify voltage as over-erasure cells among the adjacent memory cells,
wherein the over-erasure cells have a threshold voltage of an over-erasure state that is lower than a threshold voltage of an erasure state;
performing a pre-program operation that programs the over-erasure cells to the erasure state; and
performing the program operation on the selected memory cells.
(see US 12,087,376 B2: claim 17, lines 1-20 and LEE-7744 teachings)
Claim 11. The method of claim 10, wherein the over-erasure verify voltage has the same voltage level as a lowest threshold voltage, among the threshold voltages of the erasure state. (see US 12,087,376 B2: claim 18, lines 1-4)
Claim 12. The method of claim 10, wherein performing the pre-program operation comprises a pre-program voltage apply step of applying a pre-program voltage to the adjacent memory cells and a verify step of checking whether the adjacent memory cells are programmed to the erasure state,
wherein the pre-program operation includes a plurality of program loops, each including the pre-program voltage apply step and the verify step, and wherein the pre-program voltage increases by a step voltage whenever a program loop increases.
(see US 12,087,376 B2: claim 19, lines 1-10)
Claim 13. The method of claim 12, wherein the verify step comprises checking whether the adjacent memory cells are programmed to the erasure state by using the over-erasure verify voltage, and
wherein the over-erasure verify voltage has the same voltage level as a lowest threshold voltage, among the threshold voltages of the erasure state. (see US 12,087,376 B2: claim 20, lines 1-7)
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
SHIRAKAWA et al. (US 2020/0098432 A1) is applicable for all claims: teaches a memory device (para [0036], Fig. 1: 100 flash memory. See Fig. 1-Fig. 26 for illustrated components and functionality) comprising: a plurality of memory cells connected to each word line, among a plurality of word lines (see e.g. Fig. 2: WL’s and MT’s); a peripheral circuit (non-array circuitry in Fig. 1: 100) configured to perform a program operation on memory cells that are connected to a selected word line, among the plurality of word lines (para [0101]); and a control logic (Fig. 1: 200) configured to control the peripheral circuit (para [0048]) to perform the program operation (write operation of Fig. 14 and Fig. 15) on the memory cells that are connected to the selected word line (Fig. 15: during t3-t4 VPGM is applied on selected WLi) after performing a pre-program operation (Fig. 15: during t1-t3’ voltages applied to selected and non-selected WL’s) that increases a threshold voltage of over-erasure cells (Fig. 15: Vcut1 & VPGM_L, Vcut2 & Vpass are applied targeting over-erased cells in selected and non-selected word lines to increase threshold voltage. See para [0110], para [0115], Fig. 9), among memory cells that are connected to an adjacent word line (Fig. 15: non-selected cells with WL (i+-1) uses Vcut2 & Vpass), having a threshold voltage of an over- erasure state that is lower than a threshold voltage of an erasure state, to the threshold voltage of the erasure state (cells with non-selected word line with threshold voltage below vcut2 are over-erased and have threshold below erase state. See Fig. 9 illustration of Vcut voltage in context of para [0110]. See also para [0115], para [0131]), wherein the adjacent word line (Fig. 15: WL (i+-1)) is a word line next to the selected word line (Fig. 15: WL (i+)).
LEE (US 2020/0020403 A1): Fig. 1-Fig. 13 disclosure applicable for all claims.
US 20150364185 A1, US 20150364185 A1 are US version of foreign doc in IDS and are pertinent.
It is suggested that applicant consider all prior arts made of record.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825