Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20190386173 A1), in further view of An (US 20220149802 A1) and Jun (US 20220199468 A1).
Regarding independent claim 1, Chen teaches a method for fabricating semiconductor devices, comprising: providing a bonded structure comprising a first substrate and a second substrate (Fig. 5, 200, 300; [0082], “A transfer substrate 300 can be provided for each first carrier substrate 200.”), a device structure between the first substrate and the second substrate (Fig. 5, 10; [0084], “Each bonded assembly comprises…an array of devices 10.”), and a release layer between the device structure and the first substrate (Fig. 5, 20; [0084], “Each bonded assembly comprises…a release layer 20…”). However, Chen does not teach and a protective layer comprising silicon between the release layer and the first substrate, wherein the device structure includes a memory device formed on the second substrate; and applying laser radiation with a wavelength of about 3 micrometers (um) to about 10 um to the release layer to detach the first substrate and protective layer from the release layer; wherein the protective layer is transparent to the radiation.
However, in the same field of endeavor, An teaches a protective layer comprising silicon between the release layer and the first substrate (Fig. 11, 7; [0049], “Next, a first protection film 7 (e.g., Mo, W, Ta, Pt, Ti, TiW, TaN, TiN, SiO.sub.2, Al.sub.2O.sub.3, SiC, SiCN, SiN.sub.x, AlN, polyimide, BCB, SU-8, or SOG) is formed…”), and applying laser radiation with a wavelength of about 3 micrometers (um) to about 10 um to the release layer to detach the first substrate and protective layer from the release layer (Fig. 10, 1, 3; [0049], “The sapphire substrate 1 is separated by LLO.”, [0047], “Therefore, the sacrificial layer 3 comprising a single layer of GaN and Al.sub.zGa.sub.1-zN with less than 50% of Al content or their multilayer microstructure can be easily removed by a high-power single wavelength laser light source (248 nm or higher) used universally.”); wherein the protective layer is transparent to the radiation (Next, a first protection film 7 (e.g., Mo, W, Ta, Pt, Ti, TiW, TaN, TiN, SiO.sub.2, Al.sub.2O.sub.3, SiC, SiCN, SiN.sub.x, AlN, polyimide, BCB, SU-8, or SOG), (Polyimide is transparent to infrared radiation)), and Jun teaches wherein the device structure includes a memory device formed on the second substrate ([0063], “In an embodiment, device structure 104 includes a transistor, a transistor coupled with a non-volatile memory element, or a capacitor.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method of Chen with the protective layer and laser radiation of An so that “the device can have a chemically and structurally stable face” (An, [0049]), and the memory device of Jun so as to store electronic data (Jun, [0131]).
Regarding dependent claim 3, Chen, as previously modified by An and Jun, teaches the method of claim 1, and further teaches wherein the step of providing a bonded structure comprises bonding the device structure to the second substrate through an oxide layer (Fig. 4, 30A; [0077], “In one embodiment, the first bonding material layer 30A can be a silicon oxide layer…”).
Claim(s) 2, 4, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20190386173 A1), in further view of An (US 20220149802 A1), Jun (US 20220199468 A1), and Cheng (US 20190157500 A1).
Regarding dependent claim 2, Chen, as previously modified by Jun and An, teaches the method of claim 1. However, as previously combined, they do not teach wherein the protective layer includes silicon germanium.
However, in the same field of endeavor, Cheng teaches wherein the protective layer includes silicon germanium ([0038], “In some embodiments, the sacrificial layer 102 is formed of silicon-germanium…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, and Jun with the silicon germanium layer of Cheng so that the protective layer has a melting point “less than the first melting point of the substrate” (Cheng, [0020]).
Regarding dependent claim 4, Chen, as previously modified by Jun and An, teaches the method of claim 1. However, as previously combined, they do not teach wherein after detaching the first substrate and protective layer from the release layer, the method further comprises: polishing a surface of the protective layer through a chemical-mechanical polishing (CMP) process; and epitaxially growing an additional layer from the polished surface.
However, in the same field of endeavor, Cheng teaches polishing a surface of the protective layer through a chemical-mechanical polishing (CMP) process (Fig. 2E, 103; [0042], “…the protective layer 103 is removed by a wet etching process or a polishing process, such as chemical mechanical polishing (CMP).”); and epitaxially growing an additional layer from the polished surface ([0043], “Similarly, a first electrode layer 130 and a second electrode layer 120, as shown in FIG. 1E, may be respectively formed on opposing sides of the stack of semiconductor layers 108…”, [0018], “The substrate 100 is formed of a material that is suitable for growing an epitaxial structure including semiconductor materials.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, and Jun with the polishing and layer growth of Cheng so that “the fabrication of the semiconductor device is completed” (Cheng, [0043]).
Regarding dependent claim 8, Chen, as previously modified by Jun and An, teaches the method of claim 1. However, as previously combined, they do not teach wherein after detaching the first substrate and protective layer from the release layer, the method further comprises: polishing a surface of the protective layer.
However, in the same field of endeavor, Cheng teaches wherein after detaching the first substrate and protective layer from the release layer, the method further comprises: polishing a surface of the protective layer (Fig. 2E, 103; [0042], “…the protective layer 103 is removed by a wet etching process or a polishing process, such as chemical mechanical polishing (CMP).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, and Jun with the polishing of Cheng so that “the fabrication of the semiconductor device is completed” (Cheng, [0043]).
Claim(s) 5 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20190386173 A1), in further view of An (US 20220149802 A1), Jun (US 20220199468 A1), Cheng (US 20190157500 A1), and Raring (US 9666677 B1).
Regarding dependent claim 5, Chen, as previously modified by An, Jun, and Cheng, teaches the method of claim 4. However, as previously combined, they do not teach wherein the release layer is a first release layer and the device structure is a first device structure, the method further comprising: providing a second release layer on the additional layer; and providing a second device structure on the second release layer.
However, in the same field of endeavor, Raring teaches wherein the release layer is a first release layer and the device structure is a first device structure, the method further comprising: providing a second release layer on the additional layer (Fig. 5, 502; Col 28, Lines 14-15, “The buffer layer is overlaid by the selectively removable sacrificial layer 502…”); and providing a second device structure on the second release layer (Fig. 5, 501; Col. 28, Lines 15-16, “…and the device layers 501.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, Jun, and Cheng with the second release layer and second device structure of Raring so as to reuse the substrate (Raring, Col. 28).
Regarding dependent claim 9, Chen, as previously modified by An, Jun, and Cheng, teaches the method of claim 8. However, as previously combined, they do not teach further comprising: wherein the release layer is a first release layer and the device structure is a first device structure, the method further comprising: providing a second release layer on the polished protective layer; and providing a second device structure on the second release layer.
However, in the same field of endeavor, Raring teaches wherein the release layer is a first release layer and the device structure is a first device structure, the method further comprising: providing a second release layer on the additional layer (Fig. 5, 502; Col 28, Lines 14-15, “The buffer layer is overlaid by the selectively removable sacrificial layer 502…”); and providing a second device structure on the second release layer (Fig. 5, 501; Col. 28, Lines 15-16, “…and the device layers 501.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, Jun, and Cheng with the second release layer and second device structure of Raring so as to reuse the substrate (Raring, Col. 28).
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20190386173 A1), in further view of An (US 20220149802 A1), Jun (US 20220199468 A1), Raring (US 9666677 B1), and Tanabe (US 20260179877 A1).
Regarding dependent claim 6, Chen, as previously modified by An and Jun, teaches the method of claim 1. However, as previously combined, they do not teach further comprising: removing the protective layer to expose a surface of the first substrate; planarizing the surface of the first substrate through a gas cluster beam (GCB) process.
However, in the same field of endeavor, Raring teaches removing the protective layer to expose a surface of the first substrate (Col. 13, Lines 50-52, “A substrate 100 is overlaid by a buffer layer 101, a selectively removable sacrificial layer 107”, Col. 28, Lines 24-25, “Finally, the buffer layer is removed by lapping, polishing and chemical mechanical polishing (CMP)…”); and Tanabe teaches planarizing the surface of the first substrate through a gas cluster beam (GCB) process (Fig. 1, 102; [0041], “The etching apparatus (processing chamber 102) may be a gas cluster beam irradiation apparatus for irradiating the surface of a substrate W with a gas cluster beam (GCB).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, and Jun with the removal of the protective layer of Raring so that “the semiconductor substrate surface is returned to an equivalent condition as before the epitaxial growth.” (Raring, Col. 28, Lines 26-27), and the gas cluster beam of Tanabe so as to peel layers from the substrate (Tanabe, [0054]).
Regarding dependent claim 7, Chen, as previously modified by An, Jun, Raring, and Tanabe, teaches the method of claim 6. However, as previously combined, they do not teach wherein the release layer is a first release layer and the device structure is a first device structure, the method further comprising: providing a second release layer on the polished protective layer; and providing a second device structure on the second release layer.
However, in the same field of endeavor, Raring teaches wherein the release layer is a first release layer and the device structure is a first device structure, the method further comprising: providing a second release layer on the additional layer (Fig. 5, 502; Col 28, Lines 14-15, “The buffer layer is overlaid by the selectively removable sacrificial layer 502…”); and providing a second device structure on the second release layer (Fig. 5, 501; Col. 28, Lines 15-16, “…and the device layers 501.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, Jun, Raring, and Tanabe with the second release layer and second device structure of Raring so as to reuse the substrate (Raring, Col. 28).
Claim(s) 25-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20190386173 A1), in further view of An (US 20220149802 A1) and Jun (US 20220199468 A1), Cheng (US 20190157500 A1), and Raring (US 9666677 B1).
Regarding dependent claim 25, Chen, as previously modified by An and Jun, teaches the method of claim 1. However, as previously combined, they do not teach wherein the release layer is a first release layer, the protective layer is a first protective layer and the device structure is a first device structure, the method further comprising: removing the first protective layer to expose a surface of the first substrate; providing a second protective layer on the first substrate; providing a second release layer on the first substrate; and providing a second device structure on the second release layer.
However, in the same field of endeavor, Raring teaches wherein the release layer is a first release layer, the protective layer is a first protective layer and the device structure is a first device structure, the method further comprising: removing the first protective layer to expose a surface of the first substrate (Col. 13, Lines 50-52, “A substrate 100 is overlaid by a buffer layer 101, a selectively removable sacrificial layer 107”, Col. 28, Lines 24-25, “Finally, the buffer layer is removed by lapping, polishing and chemical mechanical polishing (CMP)…”); providing a second protective layer on the first substrate (Col. 28, Lines 11-13, “An epitaxial process is carried out where a buffer-layer 503 is deposited with a thickness between 1 and 50 microns.”); providing a second release layer on the first substrate (Fig. 5, 502; Col 28, Lines 14-15, “The buffer layer is overlaid by the selectively removable sacrificial layer 502…”); and providing a second device structure on the second release layer (Fig. 5, 501; Col. 28, Lines 15-16, “…and the device layers 501.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, and Jun with the layers of Raring so as to reuse the substrate (Raring, Col. 28).
Regarding dependent claim 26, Chen, as previously modified by An and Jun, teaches the method according to claim 1. However, as previously combined, they do not teach wherein the release layer is a first release layer, the device structure is a first device structure and, after detaching the first substrate and protective layer from the release layer, the method further comprises: providing a second release layer on the protective layer; and providing a second device structure on the second release layer.
However, in the same field of endeavor, Raring teaches wherein the release layer is a first release layer, the device structure is a first device structure and, after detaching the first substrate and protective layer from the release layer, the method further comprises: providing a second release layer on the protective layer (Fig. 5, 502; Col 28, Lines 14-15, “The buffer layer is overlaid by the selectively removable sacrificial layer 502…”); and providing a second device structure on the second release layer (Fig. 5, 501; Col. 28, Lines 15-16, “…and the device layers 501.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, and Jun with the layers of Raring so as to reuse the substrate (Raring, Col. 28).
Regarding dependent claim 27, Chen, as previously modified by An and Jun teaches the method of claim 1. However, as previously combined, they do not teach wherein the release layer is a first release layer, the device structure is a first device structure and, after detaching the first substrate and protective layer from the release layer, the method further comprises: polishing a surface of the protective layer; providing a second release layer on the protective layer; and providing a second device structure on the second release layer.
However, in the same field of endeavor, Cheng teaches wherein the release layer is a first release layer, the device structure is a first device structure and, after detaching the first substrate and protective layer from the release layer, the method further comprises: polishing a surface of the protective layer (Fig. 2E, 103; [0042], “…the protective layer 103 is removed by a wet etching process or a polishing process, such as chemical mechanical polishing (CMP).”); and Raring teaches providing a second release layer on the protective layer (Fig. 5, 502; Col 28, Lines 14-15, “The buffer layer is overlaid by the selectively removable sacrificial layer 502…”); and providing a second device structure on the second release layer (Fig. 5, 501; Col. 28, Lines 15-16, “…and the device layers 501.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, and Jun with the polishing of Cheng so that “the fabrication of the semiconductor device is completed” (Cheng, [0043]), and the layers of Raring so as to reuse the substrate (Raring, Col. 28).
Regarding dependent claim 28, Chen, as previously modified by An and Jun teaches the method of claim 1. However, as previously combined, they do not teach wherein the release layer is a first release layer, the protective layer is a first protective layer and the device structure is a first device structure, after detaching the first substrate and protective layer from the release layer, the method further comprises: providing a second protective layer on the first protective layer; providing a second release layer on the protective layer; and providing a second device structure on the second release layer.
However, in the same field of endeavor, Raring teaches wherein the release layer is a first release layer, the protective layer is a first protective layer and the device structure is a first device structure, after detaching the first substrate and protective layer from the release layer, the method further comprises: providing a second protective layer on the first protective layer (Col. 28, Lines 11-13, “An epitaxial process is carried out where a buffer-layer 503 is deposited with a thickness between 1 and 50 microns.); providing a second release layer on the protective layer (Fig. 5, 502; Col 28, Lines 14-15, “The buffer layer is overlaid by the selectively removable sacrificial layer 502…”); and providing a second device structure on the second release layer (Fig. 5, 501; Col. 28, Lines 15-16, “…and the device layers 501.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, and Jun with the layers of Raring so as to reuse the substrate (Raring, Col. 28).
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20190386173 A1), in further view of Raring (US 9666677 B1), Jun (US 20220199468 A1), and Cheng (US 20190157500 A1).
Regarding independent claim 10, Chen teaches a method for fabricating semiconductor devices, comprising: providing a bonded structure comprising a first substrate bonded to a second substrate (Fig. 5, 200, 300; [0082], “A transfer substrate 300 can be provided for each first carrier substrate 200.”), a device structure provided between the first substrate and the second substrate (Fig. 5, 10; [0084], “Each bonded assembly comprises…an array of devices 10.”), and a stack of layers including a release layer between the device structure and the first substrate (Fig. 5, 20; [0084], “Each bonded assembly comprises…a release layer 20…”); and applying radiation to the release layer to detach the first substrate from the release layer ([0108], “The process of selectively removing the first portions of the release layer 20 while not removing the second portions of the release layer 20 is herein referred to as an area-selective laser lift-off process or a die-selective laser lift-off process.”). However, Chen does not teach including a memory device, planarizing first substrate; and reusing the first substrate for a subsequent bonding process, wherein the subsequent bonding process includes bonding another device structure to the first substrate through another release layer, and wherein the stack of layers includes at least one of silicon carbonitride or silicon germanium.
However, in the same field of endeavor, Jun teaches including a memory device ([0063], “In an embodiment, device structure 104 includes a transistor, a transistor coupled with a non-volatile memory element, or a capacitor.”), Raring teaches planarizing first substrate (Col. 28, Lines 4-7, “In this invention the substrate can be recycled by reconditioning the surface to an epi-ready state using a combination of one or more of lapping, polishing and chemical mechanical polishing.”, Col. 28, Lines 30-34, “Progressively smaller particle sizes would be used to first planarize the wafer surface…”); and reusing the first substrate for a subsequent bonding process (Col. 27, 47-49, “…thereby allowing the substrate to be reclaimed and reused for the growth of more devices.”), wherein the subsequent bonding process includes bonding another device structure to the first substrate through another release layer (Col. 28, Lines 55-58, “With the basics of the invention describing the transfer of the gallium and nitrogen containing device layers from the bulk gallium and nitrogen containing substrate to a carrier wafer using a PEC undercut and bonding technology…”), and Cheng teaches wherein the stack of layers includes at least one of silicon carbonitride or silicon germanium ([0038], “In some embodiments, the sacrificial layer 102 is formed of silicon-germanium…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the method of Chen with the memory device of Jun so as to store electronic data (Jun, [0131]), the planarization and reuse of the substrate of Raring so as to recycle it “more than 10 times without significant change in thickness” (Raring, Col. 28, Line 50), and the silicon germanium of Cheng so that the protective layer has a melting point “less than the first melting point of the substrate” (Cheng, [0020]).
Regarding dependent claim 11, Chen, as previously modified by Jun, Raring, and Cheng, teaches the method of claim 10. However, as previously combined, they do not teach wherein the first substrate comprises a base substrate and a protective layer between the base substrate and the release layer, the method further comprising planarizing at least a portion of the protective layer.
However, Raring further teaches wherein the first substrate comprises a base substrate and a protective layer between the base substrate and the release layer, the method further comprising planarizing at least a portion of the protective layer (Col. 13, Lines 50-52, “A substrate 100 is overlaid by a buffer layer 101, a selectively removable sacrificial layer 107”, Col. 28, Lines 24-25, “Finally, the buffer layer is removed by lapping, polishing and chemical mechanical polishing (CMP)…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the method as described by Chen, Jun, Raring, and Cheng with the layers of Raring so that “substrate thickness is not reduced after lapping and CMP” (Raring, Col. 28, Lines 46-47, “Finally, the buffer layer is removed by lapping, polishing and chemical mechanical polishing (CMP)…”).
Regarding dependent claim 12, Chen, as previously modified by Jun, Raring, and Cheng, teaches the method of claim 10. However, as previously combined, they do not teach wherein the first substrate comprises a base substrate and a protective layer between the base substrate and the release layer, the method further comprising removing the protective layer and planarizing the base substrate.
However, Raring further teaches wherein the first substrate comprises a base substrate and a protective layer between the base substrate and the release layer, the method further comprising removing the protective layer and planarizing the base substrate (Col. 13, Lines 50-52, “A substrate 100 is overlaid by a buffer layer 101, a selectively removable sacrificial layer 107”, Col. 28, Lines 24-25, “Finally, the buffer layer is removed by lapping, polishing and chemical mechanical polishing (CMP)…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the method as described by Chen, Jun, Raring, and Cheng with the layers of Raring so that “substrate thickness is not reduced after lapping and CMP” (Raring, Col. 28, Lines 46-47).
Claim(s) 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 20190386173 A1), in further view of Raring (US 9666677 B1), Jun (US 20220199468 A1), Cheng (US 20190157500 A1), and An (US 20220149802 A1).
Regarding dependent claim 13, Chen, as previously modified by Raring, Jun, and Cheng, teaches the method of claim 11. Cheng further teaches wherein the protective layer includes silicon germanium or another semiconductor material transparent to infrared laser light with a wavelength of about 2 micrometers (pm) to about l0um ([0038], “In some embodiments, the sacrificial layer 102 is formed of silicon-germanium…”). However, as previously combined, they do not teach and the radiation includes infrared laser light with a wavelength of about 2 micrometers (um) to about 10um.
However, in the same field of endeavor, An teaches and the radiation includes infrared laser light with a wavelength of about 2 micrometers (um) to about 10um ([0047], “Therefore, the sacrificial layer 3 comprising a single layer of GaN and Al.sub.zGa.sub.1-zN with less than 50% of Al content or their multilayer microstructure can be easily removed by a high-power single wavelength laser light source (248 nm or higher) used universally.”, (248 nm or higher necessarily includes the given range)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the method as described by Chen, Jun, Raring, and Cheng with the wavelength of An so that the protective layer “can be easily removed” (An, [0047]).
Regarding dependent claim 14, Chen, as previously modified by Raring, Jun, Cheng, and An, teaches the method of claim 13. However, as previously combined, they do not teach further comprising: polishing a surface of the protective layer through a chemical-mechanical polishing (CMP) process to form a polished protective layer and epitaxially growing an additional layer on the polished protective layer.
However, in the same field of endeavor, Cheng teaches polishing a surface of the protective layer through a chemical-mechanical polishing (CMP) process (Fig. 2E, 103; [0042], “…the protective layer 103 is removed by a wet etching process or a polishing process, such as chemical mechanical polishing (CMP).”); and epitaxially growing an additional layer from the polished surface ([0043], “Similarly, a first electrode layer 130 and a second electrode layer 120, as shown in FIG. 1E, may be respectively formed on opposing sides of the stack of semiconductor layers 108…”, [0018], “The substrate 100 is formed of a material that is suitable for growing an epitaxial structure including semiconductor materials.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, Jun, Raring, and Cheng with the polishing and layer growth of Cheng so that “the fabrication of the semiconductor device is completed” (Cheng, [0043]).
Claim(s) 18-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Raring (US 9666677 B1), in further view of Chen (US 20190386173 A1), An (US 20220149802 A1), Jun (US 20220199468 A1), and Cheng (US 20190157500 A1).
Regarding independent claim 18, Raring teaches a method for fabricating semiconductor devices, comprising: providing a substrate having structural damage caused by exposure to a radiation source in a first bonding process, the structural damage including an intermittent, semi-regular, or regular array of peaks (Col. 28, Lines 32-33, “…subsurface damage to the crystal induced by the initial removal process.”); and planarizing the substrate by flattening or removing the peaks (Col. 28, Lines 30-33, “Progressively smaller particle sizes would be used to first planarize the wafer surface and then remove subsurface damage to the crystal induced by the initial removal process.”). However, Raring does not teach and providing and processing a series of layers on the planarized substrate to form a device structure including a memory device, the stack of layers including a protection layer and a release layer, at least one of the layers in the stack of layers including silicon carbonitride.
However, in the same field of endeavor, Chen teaches providing and processing a series of layers on the planarized substrate to form a device structure (Fig. 5, 10; [0084], “Each bonded assembly comprises…an array of devices 10.”), the stack of layers including a release layer (Fig. 5, 20; [0084], “Each bonded assembly comprises…a release layer 20…”), An teaches the stack of layers including a protection layer, at least one of the layers in the stack of layers including silicon carbonitride (Fig. 11, 7; [0049], “Next, a first protection film 7 (e.g., Mo, W, Ta, Pt, Ti, TiW, TaN, TiN, SiO.sub.2, Al.sub.2O.sub.3, SiC, SiCN, SiN.sub.x, AlN, polyimide, BCB, SU-8, or SOG) is formed…”), and Jun teaches including a memory device ([0063], “In an embodiment, device structure 104 includes a transistor, a transistor coupled with a non-volatile memory element, or a capacitor.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the fabrication method of Raring with the layers of Chen so as to “provide sufficient adhesion to the substrate” (Chen, [0080]), the layers of An so that “the device can have a chemically and structurally stable face” (An, [0049]), and the memory device of Jun so as to store electronic data (Jun, [0131]).
Regarding dependent claim 19, Raring, as previously modified by Chen, An, and Jun, teaches the method of claim 18. However, as previously combined, they do not teach wherein the substrate includes silicon or silicon germanium and utilizing the substrate comprises epitaxially growing an additional layer of silicon or silicon germanium over the substrate.
However, in the same field of endeavor, Cheng teaches wherein the substrate includes silicon or silicon germanium ([0005], “Comparing the silicon carbide substrate…”) and utilizing the substrate comprises epitaxially growing an additional layer of silicon or silicon germanium over the substrate ([0038], “In some embodiments, the sacrificial layer 102 is formed of silicon-germanium…”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the method as described by the combination of Chen, An, and Jun with the silicon germanium layer of Cheng so that the protective layer has a melting point “less than the first melting point of the substrate” (Cheng, [0020]).
Regarding dependent claim 20, Raring, as previously modified by Chen, An, and Jun, teaches the method of claim 18, and further teaches wherein the substrate includes a base substrate and a base protective layer (Col. 13, Lines 50-52, “A substrate 100 is overlaid by a buffer layer 101, a selectively removable sacrificial layer 107”).
Regarding dependent claim 21, Raring, as previously modified by Chen, An, and Jun, teaches the method of claim 20, and further teaches wherein the base protective layer is removed and planarizing the substrate comprises planarizing the base substrate (Col. 28, Lines 24-25, “Finally, the buffer layer is removed by lapping, polishing and chemical mechanical polishing (CMP)…”).
Regarding dependent claim 22, Raring, as previously modified by Chen, An, and Jun, teaches the method of claim 20, and further teaches wherein planarizing the substrate comprises planarizing the base protective layer (Col. 28, Lines 24-25, “Finally, the buffer layer is removed by lapping, polishing and chemical mechanical polishing (CMP)…”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220093579 A1,.
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/TIMOTHY JAMES MATTABONI/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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