Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-2, 4-5, 8, 10-11, 14-16, and 18-19 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Si et al. US Pub. No. 20150102849 also see Fig. 9 of Tandon et al.
It is noted that the structure of the level shifter circuit in Fig. 4 of Si suggested by the reference is identical to Fig. 9 of the present invention, therefore, the function may be inherent or intrinsic to the structure by its property or its characteristic as rejected below.
As per claims 1, 4-5, 8, 14-16, and 18-19, Fig. 4 of Si is directed to a level shift circuit, comprising: a first NMOS differential pair (401 and 402)( coupled to a ground rail (VSS); a differential input (SAMD1 and SAMB1) driving the first NMOS differential pair; a second NMOS differential pair (403 and 404) in series with the first NMOS differential pair; a first PMOS differential pair (407 AND 408) coupled to a voltage supply (VPP), wherein the first PMOS differential pair is cross-coupled (Fig. 4); a second PMOS differential pair (405 and 406) in series with the first PMOS differential pair; a first differential output (P1 and P2) coupled between the second NMOS differential pair and the second PMOS differential pair; a second differential output (SAHB and SAHD) coupled between the first PMOS differential pair and the second PMOS differential pair; an ngate bias line (VMIDN) driving the second NMOS differential pair with a first voltage (VMIDN, 1.65V, par. 31) that is an overdrive voltage (Vod) greater than a second voltage (Vx=1.45V, par. 31 or 37, Fig. 3) used by the differential input to drive the first NMOS differential pair; and a pgate bias line driving the second PMOS differential pair with a first voltage (1.65 V, par. 47) that is an Vod less than a second voltage (1.85 V, par. 47) that is used by the second differential output to drive the first PMOS differential pair; wherein each of the first NMOS differential pair, the second NMOS differential pair, the first PMOS differential pair, and the second PMOS differential pair comprises a pair of core devices (NMOSs OR PMOSs), and wherein the voltage supply is greater than a breakdown voltage (punch-through voltage, 2.4 V, abstract, par. 43 or 44) of each core device
As per claims 2, 10, and 11, Fig. 4 of Si discloses wherein: in a first state, the differential input is configured to drive each of the first differential output and the second differential output to a first level of the voltage supply (Fig. 4); and in a second state, the differential input is configured to: drive the first differential output to a second level of the ground rail (Fig. 4); and drive the second differential output to a midpoint level between the first level and the second level (Fig. 4).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
7. Claims 3, 9 and 17 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Si et al. US Pub. No. 20150102849 in view of Viani US Pub. No. 20140218070.
Fig. 4 of Si discloses wherein the voltage supply is a first voltage supply, but fails to disclose wherein the second differential output drives a pair of buffers coupled between the voltage supply and a second voltage supply. However, 3 of Viani discloses the second differential output (Vlatch and Vlatch_p) drives a pair of buffers (130 and135) coupled between the voltage supply (Vdd2) and a second voltage supply (Vss2). the second differential output drives a pair of buffers coupled between the voltage supply and a second voltage supply. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Si’s level shifter circuit which utilizes the pair of buffers as taught by in order to connect to invert the logic state of the second differential output (par. 4).
8. Claims 6, 12 and 20 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Si et al. US Pub. No. 20150102849 in view Duby US Pub. No. 10256820 or Mn2 and M’n2 of Fig. 6 or Mp1-Mp7 and M’p1-M’p7 of Fig. 7 of Lee et al. US Patent No. 5821800.
Fig. 4 of Si fails to disclose further comprising a third NMOS differential pair in series with the first NMOS differential pair and the second NMOS differential pair. However, Fig. 2B of Duby discloses a third NMOS differential pair (N2 and N5) in series with the first NMOS differential pair (N0 and N1) and the second NMOS differential pair (N3 and N6). It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Si’s level shifter circuit to add the third NMOS difference pair as taught by Duby in order to reduce a gate voltage of the thin oxide PMOS (claim 1).
9. Claims 7 and 13 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Si et al. US Pub. No. 20150102849 in view Yabe US Patent No. 11405039 or Mp1 and M’p1 of Fig. 6 or Mn2-Mn7 and M’n2-M’n7 of Fig. 7 of Lee et al. US Patent No. 5821800.
Fig. 4 of Si fails to disclose further comprising a third PMOS differential pair in series with the first PMOS differential pair and the second PMOS differential pair. However, column 14, lines 21-27 of Yabe discloses two or more PMOS devices connected in series. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Si’s level shifter circuit to add more PMOS difference pair as taught by Yabe in order to switch speed (col. 14, line 33-34).
10. The prior art made of record and not relied upon is considered pertinent to applicants’ disclosure. Note the additional references cited on the attached PTO-892 form which show further examples of the level shifter circuit.
11. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
12. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Hoai V. Ho whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Monday through Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827