DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Domestic Benefit
This application is a continuation of Application No. 18/361,758, filed July 28, 2023, now U.S. Patent No. 12,100,753, which is a continuation of Application No. 17/111,427, filed December 3, 2020, now U.S. Patent No. 11,757,025, which is a continuation of Application No. 16/142,890, filed September 26, 2018, now U.S. Patent No. 10,868,157.
The effective filing date accorded the claims is September 26, 2018.
Claims 1–20 are pending and have been examined.
Foreign Priority
No claim to a foreign application for foreign priority.
Information Disclosure Statement
The information disclosure statement submitted on 10/07/2024 was filed before first Office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered.
Status of Claims
Claims 1–20 are rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 8, 18, 19, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 7 and 18, each recites “a metal layer surrounding at least a portion of the fin and between the gate electrode and the gate dielectric layer.” It is unclear what is required to be “between the gate electrode and the gate dielectric layer.” The phrase can be read as (i) the metal layer is between the gate electrode and the gate dielectric layer, or (ii) the surrounding relationship and the “between” relationship are two separate requirements with no clear subject for “between.” Clarification is required (for example: “a metal layer surrounding at least a portion of the fin, the metal layer being between the gate electrode and the gate dielectric layer”).
Regarding claims 8 and 19, each recites “formed of a same layer of dielectric material.” The article “a” together with “same” does not have a clear antecedent relationship to the previously recited “tunnel diode dielectric layer” and “gate dielectric layer.” It is unclear whether the two dielectric layers are required to be regions of one continuous film, or two films of identical composition formed separately. Clarification is required (for example: “formed of the same layer of dielectric material”).
Regarding claim 20, the claim recites a method of “controlling a negative transconductance behavior of a sensing tunnel diode” and then recites:
wherein:
applying the voltage to the gate electrode of the control tunnel diode includes biasing the gate electrode of the control tunnel diode from an inversion region to a flat band region; or
controlling the negative transconductance behavior of the sensing tunnel diode includes modulating a Schottky barrier height of the sensing tunnel diode.
It is unclear whether the “or” clause is (i) an alternative limitation on how the controlling step is performed, or (ii) an alternative to the applying step. As written, one of ordinary skill cannot determine which steps are required. Further, “negative transconductance behavior” is recited as a result without an objective standard in the claim for when that behavior is or is not present.
For purposes of applying art and double patenting:
Claims 7 and 18 are treated as requiring that the metal layer surrounds at least a portion of the fin and that the metal layer is between the gate electrode and the gate dielectric layer.
Claims 8 and 19 are treated as requiring that the tunnel diode dielectric layer and the gate dielectric layer are portions of one dielectric film.
Claim 20 is treated as a method of applying a gate bias from inversion toward flat-band so as to modulate the Schottky barrier height of the adjacent sensing tunnel diode.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
I. Nonstatutory obviousness-type double patenting over U.S. Patent No. 12,100,753
Claims 1–3, 5–10, 12–14, and 16–19 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims of U.S. Patent No. 12,100,753.
Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant claims
U.S. Patent No. 12,100,753
1 (first alternative: gate dielectric is SiO2/HfO2)
1 + 3 + 4
2
1 + 2 + 3 + 4
3
1 + 3 + 4
5
1 + 3 + 4 + 6
6
1 + 3 + 4
7
1 + 3 + 4 + 7
8
1 + 3 + 4 + 7 + 8
9
1 + 3 + 4 + 10
10
1 + 3 + 4 + 11
12
1 + 9
13
1 + 2 + 9
14
1 + 3 + 9
16
1 + 6 + 9
17
1 + 9
18
1 + 7 + 9
19
1 + 7 + 8 + 9
Claims 4, 11, 15, and 20 of the instant application are not rejected on the ground of nonstatutory double patenting over U.S. Patent No. 12,100,753. Issued claim 5 recites that the gate electrode is a TaN/TiAl/Al stack, not that the tunnel diode electrode is that stack. Issued independent claim 12 is a separate fingers device and is not combined with issued claim 1. Issued claims 18–20 are methods of forming, not methods of applying a voltage and controlling negative transconductance.
Patented claim 1 recites a device comprising a substrate having a surface; a tunnel diode dielectric layer on the surface of the substrate; a tunnel diode electrode on the tunnel diode dielectric layer; a gate dielectric layer on the surface of the substrate adjacent to the tunnel diode dielectric layer, the gate dielectric layer having a thickness that is greater than a thickness of the tunnel diode dielectric layer; a gate electrode on the gate dielectric layer; and a substrate electrode on the surface of the substrate, the tunnel diode electrode positioned between the gate electrode and the substrate electrode.
Patented claim 3 recites that the tunnel diode dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer.
Patented claim 4 recites that the gate dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer.
Instant claim 1 recites the same electrode arrangement and, in the first alternative, that the gate dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine patented claims 1, 3, and 4 for the purpose of providing an optimum device. Claim 3 specifies the composition of the tunnel diode dielectric layer already recited in claim 1. Claim 4 specifies the composition of the gate dielectric layer already recited in claim 1. One of ordinary skill would combine those dependents with claim 1 because they recite the materials of layers already required by claim 1. The combination includes every element of the first alternative of instant claim 1. Patented claim 1 also requires that the gate dielectric layer is thicker than the tunnel diode dielectric layer. That additional limitation does not patentably distinguish the claims. Instant claim 1 is a genus of the patented species.
The remaining rejected instant claims add only features already present, in the same words, in the corresponding patented dependent claims.
II. Nonstatutory obviousness-type double patenting over U.S. Patent No. 11,757,025
Claims 1–3, 5–9, 11–14, and 16–19 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims of U.S. Patent No. 11,757,025.
Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant claims
U.S. Patent No. 11,757,025
1 (first alternative: gate dielectric is SiO2/HfO2)
1 + 4
2
1 + 2 + 4
3
1 + 3 + 4
5
1 + 4 + 7
6
1 + 4 + 8
7
1 + 4 + 9
8
1 + 4 + 9 + 10
9
1
11
1 + 12
12
1 + 11
13
1 + 2 + 11
14
1 + 3 + 11
16
1 + 7 + 11
17
1 + 8 + 11
18
1 + 9 + 11
19
1 + 9 + 10 + 11
Claims 4, 10, 15, and 20 of the instant application are not rejected on the ground of nonstatutory double patenting over U.S. Patent No. 11,757,025. This patent has no device claim that both the tunnel diode electrode and the gate electrode are TaN/TiAl/Al stacks. Issued independent claim 13 recites a plurality of gate electrodes but does not recite a substrate electrode. Issued claims 18–20 are methods of forming, not methods of applying a voltage and controlling negative transconductance.
Patented claim 1 recites a device comprising a substrate; a tunnel diode dielectric layer on the substrate; a tunnel diode electrode on the tunnel diode dielectric layer; a gate dielectric layer on the substrate adjacent to the tunnel diode dielectric layer; a gate electrode on the gate dielectric layer; and a substrate electrode on the substrate, the tunnel diode electrode positioned between the gate electrode and the substrate electrode, wherein the tunnel diode electrode laterally surrounds a periphery of the gate electrode.
Patented claim 4 recites that the gate dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine patented claims 1 and 4 for the purpose of providing an optimum device. Claim 4 specifies the composition of the gate dielectric layer already recited in claim 1. The combination includes every element of the first alternative of instant claim 1. Patented claim 1 also requires that the tunnel diode electrode laterally surrounds a periphery of the gate electrode. That additional limitation does not patentably distinguish the claims. Instant claim 1 is a genus of the patented species. Instant claim 9 is the surrounding limitation already in patented claim 1.
The remaining rejected instant claims add only features already present, in the same words, in the corresponding patented dependent claims.
III. Nonstatutory obviousness-type double patenting over U.S. Patent No. 10,868,157
Claims 1–20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims of U.S. Patent No. 10,868,157.
Although the claims at issue are not identical, they are not patentably distinct from each other.
Instant claims
U.S. Patent No. 10,868,157
1 (first alternative)
1 + 3
1 (second alternative)
1 + 4
2
1 + 2 + 3 or 1 + 2 + 4
3
1 + 3
4
1 + 4 + 5
5
1 + 3 + 6 or 1 + 4 + 6
6
1 + 3 + 7 or 1 + 4 + 7
7
1 + 3 + 8 or 1 + 4 + 8
8
1 + 3 + 8 + 9 or 1 + 4 + 8 + 9
9
1 + 3 + 11 or 1 + 4 + 11
10
1 + 3 + 12 or 1 + 4 + 12
11
1 + 3 + 13 or 1 + 4 + 13
12
1 + 10
13
1 + 2 + 10
14
1 + 10
15
1 + 4 + 5 + 10
16
1 + 6 + 10
17
1 + 7 + 10
18
1 + 8 + 10
19
1 + 8 + 9 + 10
20
17 + 18 or 17 + 19
Patented claim 1 recites a device comprising a substrate having a surface; a tunnel diode dielectric layer on the surface of the substrate; a tunnel diode electrode on the tunnel diode dielectric layer; a gate dielectric layer on the surface of the substrate adjacent to the tunnel diode dielectric layer; a gate electrode on the gate dielectric layer; and a substrate electrode on the surface of the substrate, the tunnel diode electrode positioned between the gate electrode and the substrate electrode, wherein the substrate has a substantially same composition at the surface of the substrate underlying and extending between the tunnel diode electrode and the gate electrode, and wherein the tunnel diode dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer.
Patented claim 3 recites that the gate dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer.
Patented claim 4 recites that the tunnel diode electrode is a multi-layer stack including tantalum nitride (TaN), titanium aluminide (TiAl), and aluminum (Al).
Patented claim 5 recites that the gate electrode is a multi-layer stack including TaN, TiAl, and Al.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine patented claims 1 and 3, and separately to combine patented claims 1 and 4 for the purpose of an optimum device.
Claim 3 specifies the composition of the already-recited gate dielectric layer of claim 1. The combination of claims 1 and 3 includes every element of the first alternative of instant claim 1 (“the gate dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer”).
Claim 4 specifies the composition of the already-recited tunnel diode electrode of claim 1. The combination of claims 1 and 4 includes every element of the second alternative of instant claim 1 (“the tunnel diode electrode is a multi-layer stack including tantalum nitride (TaN), titanium aluminide (TiAl), and aluminum (Al)”).
One of ordinary skill would combine those dependents with claim 1 because they recite the materials of layers already present in claim 1 and because the combination form an optimum device. Patented claim 1 also requires a substantially same surface composition and that the tunnel diode dielectric layer is SiO2/HfO2. Those additional limitations do not patentably distinguish the claims.
Instant claim 4 is patented claims 1+4+5 (both electrodes TaN/TiAl/Al).
Instant claim 20 is patented claims 17+18 or 17+19. Patented claim 17 recites applying a voltage to a gate electrode of a control tunnel diode and controlling a negative transconductance behavior of a sensing tunnel diode adjacent to the control tunnel diode, with the same sensing-tunnel-diode / control-tunnel-diode / substrate-electrode layout. Patented claim 18 recites biasing from an inversion region to a flat band region. Patented claim 19 recites modulating a Schottky barrier height of the sensing tunnel diode. Instant claim 20 recites those two limitations in the alternative.
A terminal disclaimer over U.S. Patent Nos. 12,100,753, 11,757,025, and 10,868,157 is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
References applied
Liao et al., “Remote Gate-Controlled Negative Transconductance in Gated MIS Tunnel Diode,” IEEE Transactions on Electron Devices, Vol. 63, No. 7, pp. 2864–2870 (published 20 May 2016) (“Liao”).
U.S. Patent No. 8,994,124 B2 to Ogawa, issued March 31, 2015 (“Ogawa”).
U.S. Patent Application Publication No. 2016/0133470 A1 to Bordelon et al., published May 12, 2016 (“Bordelon”).
U.S. Patent No. 9,620,610 B2 to Jangjian et al., issued April 11, 2017 (“Jangjian”).
Liao is prior art under 35 U.S.C. 102(a)(1). Liao is an inventor-originated disclosure published more than one year before the effective filing date of September 26, 2018, and is not excluded by 35 U.S.C. 102(b)(1). Ogawa, Bordelon, and Jangjian are prior art under 35 U.S.C. 102(a)(1).
Claims 1–6, 9–17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liao in view of Ogawa and Bordelon.
Regarding independent claim 1, Liao teaches a device, comprising:
a substrate having a surface (Si substrate; Liao, Figs. 1–3, § II);
a tunnel diode dielectric layer on the surface of the substrate (SiO2 tunnel oxide of the sensing MIS tunnel diode; Liao, Abstract, Fig. 1, oxide thickness including 3.3 nm);
a tunnel diode electrode on the tunnel diode dielectric layer (Al electrode of the sensing MIS tunnel diode; Liao, Fig. 1, § II);
a gate dielectric layer on the surface of the substrate adjacent to the tunnel diode dielectric layer (oxide of the adjacent control MIS used as the gate; Liao, Abstract, Fig. 1);
a gate electrode on the gate dielectric layer (Al electrode of the control MIS; Liao, Fig. 1); and
a substrate electrode on the surface of the substrate, the tunnel diode electrode positioned between the gate electrode and the substrate electrode (substrate contact; the sensing MIS tunnel diode sits between the control-gate MIS and the substrate contact in the reported two-electrode-plus-substrate-contact layout; Liao, Figs. 1–3, § II).
Liao does not teach that the gate dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer, or that the tunnel diode electrode is a multi-layer stack including tantalum nitride (TaN), titanium aluminide (TiAl), and aluminum (Al).
Ogawa teaches that the gate dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer (gate insulating film 30 includes a SiO2 film 31 provided on the silicon substrate and a HfO2 film 32 provided on the SiO2 film 31; Ogawa, col. 6, ll. 15–30; thicknesses of the SiO2 film 31 of 0.4 to 1.5 nm and of the HfO2 film 32 of 0.9 to 4 nm).
Bordelon teaches that the electrode is a multi-layer stack including tantalum nitride (TaN), titanium aluminide (TiAl), and aluminum (Al) (tantalum-nitride barrier layer 24′; titanium-aluminum layer 30′ on the tantalum-nitride barrier layer; bulk aluminum layer 80′ deposited on the titanium-aluminum layer; Bordelon, Fig. 1D and Fig. 3B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the gate dielectric layer of Liao to be a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer, as taught by Ogawa, and/or to form the tunnel diode electrode of Liao as a multi-layer stack including tantalum nitride (TaN), titanium aluminide (TiAl), and aluminum (Al), as taught by Bordelon. Ogawa teaches that using a SiO2 film and a HfO2 film as the gate insulating film reduces gate leakage current (Ogawa, col. 6). Bordelon teaches the TaN / titanium-aluminum / bulk aluminum stack as a gate electrode structure on a high-k dielectric (Bordelon, Fig. 3B). Applying those materials to Liao’s control-gate dielectric and to Liao’s tunnel diode electrode, respectively, uses known dielectric and electrode stacks in Liao’s already-adjacent MIS pair and yields the predictable result of a gated MIS tunnel diode whose gate dielectric is SiO2/HfO2 or whose tunnel diode electrode is TaN/TiAl/Al. Either alternative meets claim 1.
Regarding claim 2, Liao in view of Ogawa and Bordelon teaches the device of claim 1.
Liao teaches wherein the substrate includes a doped region, wherein the substrate electrode contacts the doped region of the substrate (ohmic substrate contact to the Si wafer; Liao, Fig. 1, § II). Ogawa also teaches doped regions in the substrate contacted by electrodes (source region 21 and drain region 22 provided in the silicon substrate; Ogawa, col. 5).
Regarding claim 3, Liao in view of Ogawa and Bordelon teaches the device of claim 1.
Ogawa teaches wherein the tunnel diode dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer (SiO2 film 31 and HfO2 film 32 as the insulating film on the silicon substrate; Ogawa, col. 6). It would have been obvious to use that same SiO2/HfO2 multi-layer structure as Liao’s tunnel diode dielectric layer for the same leakage-reduction reason Ogawa gives for the gate insulating film.
Regarding claim 4, Liao in view of Ogawa and Bordelon teaches the device of claim 1.
Bordelon teaches wherein the tunnel diode electrode is a multi-layer stack including tantalum nitride (TaN), titanium aluminide (TiAl), and aluminum (Al), and the gate electrode is a multi-layer stack including TaN, TiAl, and Al (TaN barrier, titanium-aluminum layer, and bulk aluminum layer as the electrode stack; Bordelon, Fig. 1D, Fig. 3B). It would have been obvious to form both of Liao’s adjacent electrodes from that same stack so that both electrodes are made in one metal module.
Regarding claim 5, Liao in view of Ogawa and Bordelon teaches the device of claim 1.
Liao teaches wherein the tunnel diode dielectric layer has a thickness that is equal to or less than 4 nm (oxide thickness of 3.3 nm; Liao, Abstract, § III).
Regarding claim 6, Liao in view of Ogawa and Bordelon teaches the device of claim 1.
Ogawa teaches a gate dielectric layer having a thickness, and Liao teaches a tunnel diode dielectric layer having a thickness of 3.3 nm. Ogawa’s combined SiO2 (0.4 to 1.5 nm) plus HfO2 (0.9 to 4 nm) gate insulating film can be formed thicker than Liao’s 3.3 nm tunnel oxide. It would have been obvious to form the gate dielectric layer to have a thickness that is greater than a thickness of the tunnel diode dielectric layer so that the control electrode of Liao functions as a gate capacitor while the sensing electrode continues to tunnel, which is the operating mode Liao describes (Liao, §§ I–III).
Regarding claim 9, Liao in view of Ogawa and Bordelon teaches the device of claim 1.
Liao teaches a gate electrode adjacent to a tunnel diode electrode (Liao, Fig. 1). Forming the tunnel diode electrode so that the tunnel diode electrode laterally surrounds the gate electrode is a layout of that same adjacent pair. It would have been obvious to arrange Liao’s sensing electrode around Liao’s control-gate electrode to increase the facing edge length along which Liao’s peripheral minority-carrier control mechanism operates (Liao, Abstract, § I, edge Schottky diode current).
Regarding claim 10, Liao in view of Ogawa and Bordelon teaches the device of claim 1.
Liao teaches a gate electrode adjacent to a tunnel diode electrode (Liao, Fig. 1). It would have been obvious to provide a plurality of gate electrodes positioned about a periphery of the tunnel diode electrode as a duplication of Liao’s control gate around the sensing diode, to increase the edge coupling Liao identifies as the origin of the negative transconductance (Liao, Abstract, § III).
Regarding claim 11, Liao in view of Ogawa and Bordelon teaches the device of claim 1.
Liao teaches a tunnel diode electrode and a gate electrode facing one another across a gap (Liao, Fig. 1). It would have been obvious to form the tunnel diode electrode to include a plurality of fingers which extend from a body of the tunnel diode electrode toward a body of the gate electrode, and the gate electrode to include a plurality of fingers which extend from the body of the gate electrode toward the body of the tunnel diode electrode, in order to increase the facing edge length of Liao’s two electrodes and thereby increase the peripheral coupling current Liao reports (Liao, Abstract, §§ I–III).
Regarding independent claim 12, Liao teaches a device, comprising:
a substrate having a surface (Si substrate; Liao, Figs. 1–3);
a tunnel diode dielectric layer on the surface of the substrate (SiO2 of the sensing MIS tunnel diode; Liao, Fig. 1);
a tunnel diode electrode on the tunnel diode dielectric layer (Al sensing electrode; Liao, Fig. 1);
a gate dielectric layer on the surface of the substrate adjacent to the tunnel diode dielectric layer (oxide of the control MIS; Liao, Fig. 1);
a gate electrode on the gate dielectric layer (Al control-gate electrode; Liao, Fig. 1); and
a substrate electrode on the surface of the substrate, the tunnel diode electrode positioned between the gate electrode and the substrate electrode (substrate contact; Liao, Figs. 1–3).
Liao teaches that negative transconductance exists even though the separation between the gate and the MIS tunnel diode is large, up to several tens of micrometers, and also treats the close-spaced gated-MIS-tunnel-diode case (Liao, Abstract, § I). Liao therefore teaches a spacing that includes values equal to or less than 100 nm at the close-spaced end of the range Liao actually operates.
To the extent Liao is not found to expressly disclose a spacing equal to or less than 100 nm, it would have been obvious to set the gate electrode spaced apart from the tunnel diode electrode by a distance equal to or less than 100 nm because Liao teaches that the peripheral minority-carrier control mechanism is an edge effect whose strength increases as the gate is brought closer to the sensing tunnel diode (Liao, Abstract, §§ I–III).
Regarding claim 13, Liao in view of Ogawa and Bordelon teaches the device of claim 12.
Liao teaches wherein the substrate includes a doped region, wherein the substrate electrode contacts the doped region of the substrate (substrate ohmic contact; Liao, Fig. 1).
Regarding claim 14, Liao in view of Ogawa and Bordelon teaches the device of claim 12.
Ogawa teaches wherein the tunnel diode dielectric layer is a multi-layer structure including a silicon dioxide (SiO2) layer and a hafnium dioxide (HfO2) layer (SiO2 film 31 and HfO2 film 32; Ogawa, col. 6). It would have been obvious to use that multi-layer structure as the tunnel diode dielectric layer of Liao for the leakage-reduction reason stated in Ogawa.
Regarding claim 15, Liao in view of Ogawa and Bordelon teaches the device of claim 12.
Bordelon teaches wherein the tunnel diode electrode is a multi-layer stack including tantalum nitride (TaN), titanium aluminide (TiAl), and aluminum (Al), and the gate electrode is a multi-layer stack including TaN, TiAl, and Al (TaN / titanium-aluminum / bulk aluminum; Bordelon, Fig. 1D, Fig. 3B). It would have been obvious to form both of Liao’s electrodes from that stack.
Regarding claim 16, Liao in view of Ogawa and Bordelon teaches the device of claim 12.
Liao teaches wherein the tunnel diode dielectric layer has a thickness that is equal to or less than 4 nm (3.3 nm; Liao, Abstract).
Regarding claim 17, Liao in view of Ogawa and Bordelon teaches the device of claim 12.
It would have been obvious to form the gate dielectric layer to have a thickness that is greater than a thickness of the tunnel diode dielectric layer so that Liao’s control MIS operates as a gate while Liao’s sensing MIS continues to tunnel (Liao, §§ I–III; Ogawa, col. 6, SiO2 plus HfO2 gate insulating film).
Regarding independent claim 20, Liao teaches a method, comprising:
applying a voltage to a gate electrode of a control tunnel diode (sweeping VG of the separated MIS used as the gate; Liao, Abstract, Figs. 2–3); and
controlling a negative transconductance behavior of a sensing tunnel diode adjacent to the control tunnel diode, based on the voltage applied to the gate electrode of the control tunnel diode (negative transconductance of the sensing MIS tunnel diode around the flat-band region of the control gate; Liao, Abstract, §§ I–III),
wherein the sensing tunnel diode includes a tunnel oxide layer on a substrate, and a tunnel diode electrode on the tunnel oxide layer (Al / SiO2 / Si sensing TD; Liao, Fig. 1),
the control tunnel diode includes a gate oxide layer on the substrate, the gate electrode disposed on the gate oxide layer (adjacent control MIS; Liao, Fig. 1), and
a substrate electrode is disposed on a doped region of the substrate, the sensing tunnel diode positioned between the control tunnel diode and the substrate electrode (substrate contact; sensing TD between the control gate and the substrate contact; Liao, Figs. 1–3),
wherein applying the voltage to the gate electrode of the control tunnel diode includes biasing the gate electrode of the control tunnel diode from an inversion region to a flat band region (NT exists around the flat-band region; valley of the kink matches the flat-band region of the MIS tunnel gate capacitor; Liao, Abstract, Fig. 2); or
controlling the negative transconductance behavior of the sensing tunnel diode includes modulating a Schottky barrier height of the sensing tunnel diode (effective Schottky barrier height of the MIS tunnel diode is modulated by controlling the substrate surface minority carrier concentration with the gate bias; Liao, Abstract, § I).
Liao therefore teaches every limitation of claim 20. To the extent the “or” clause is read as requiring both listed alternatives, Liao teaches both (bias from inversion through flat-band, and modulation of Schottky barrier height) as the same mechanism (Liao, Abstract, §§ I–III).
Claims 7, 8, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Liao in view of Ogawa and Bordelon as applied to claims 1 and 12 above, and further in view of Jangjian.
Regarding claim 7, Liao in view of Ogawa and Bordelon teaches the device of claim 1, including a substrate having a surface, a tunnel diode dielectric layer, a tunnel diode electrode, a gate dielectric layer, a gate electrode, and a substrate electrode, the tunnel diode electrode positioned between the gate electrode and the substrate electrode.
Liao in view of Ogawa and Bordelon does not teach a fin on the surface of the substrate; a metal layer surrounding at least a portion of the fin and between the gate electrode and the gate dielectric layer; and an isolation dielectric layer between the tunnel diode electrode and the metal layer, wherein the tunnel diode dielectric layer is disposed between the fin and the tunnel diode electrode, and the gate electrode contacts the metal layer.
Jangjian teaches a fin on the surface of the substrate (semiconductor fin; Jangjian, Abstract, Fig. 1);
a metal layer surrounding at least a portion of the fin and between the gate electrode and the gate dielectric layer (n-type gate structure over a first semiconductor fin, including a work-function metal layer overlying the high-k dielectric layer and wrapping the fin; Jangjian, Abstract, claim 1); and
an isolation dielectric layer between an adjacent electrode structure and the metal layer (gate spacers isolating the gate stack; Jangjian, specification describing gate spacers on the fin gate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form Liao’s gated MIS tunnel diode on a fin, with a metal layer surrounding at least a portion of the fin and between the gate electrode and the gate dielectric layer, and with an isolation dielectric layer between the tunnel diode electrode and the metal layer, as taught by Jangjian, wherein the tunnel diode dielectric layer is disposed between the fin and the tunnel diode electrode, and the gate electrode contacts the metal layer. Jangjian teaches a FinFET gate in which the metal gate surrounds the fin over a high-k dielectric. Placing Liao’s control gate on that wrap-around metal, and placing Liao’s sensing tunnel diode electrode on the same fin separated by Jangjian’s isolation dielectric (spacer), transfers Liao’s adjacent MIS pair onto Jangjian’s fin and increases the perimeter over which Liao’s edge-controlled tunneling current flows.
Regarding claim 8, Liao in view of Ogawa, Bordelon, and Jangjian teaches the device of claim 7.
Ogawa teaches a SiO2 film and a HfO2 film formed as one gate insulating film (Ogawa, col. 6). Jangjian teaches a high-k dielectric layer on the fin (Jangjian, Abstract). It would have been obvious to form the tunnel diode dielectric layer and the gate dielectric layer of a same layer of dielectric material by depositing one dielectric film on the fin of Jangjian and using portions of that film under both of Liao’s electrodes.
Regarding claim 18, Liao in view of Ogawa and Bordelon teaches the device of claim 12.
Liao in view of Ogawa and Bordelon does not teach a fin on the surface of the substrate; a metal layer surrounding at least a portion of the fin and between the gate electrode and the gate dielectric layer; and an isolation dielectric layer between the tunnel diode electrode and the metal layer, wherein the tunnel diode dielectric layer is disposed between the fin and the tunnel diode electrode, and the gate electrode contacts the metal layer.
Jangjian teaches those fin, surrounding-metal, and isolation-dielectric limitations as set forth above for claim 7. It would have been obvious to form the device of claim 12 on the fin of Jangjian for the same reason given for claim 7.
Regarding claim 19, Liao in view of Ogawa, Bordelon, and Jangjian teaches the device of claim 18.
It would have been obvious to form the tunnel diode dielectric layer and the gate dielectric layer of a same layer of dielectric material for the same reason given for claim 8.
Conclusion
Claims 1–20 are rejected.
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15 June 2026
/John P. Dulka/Primary Examiner, Art Unit 2817
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