DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publications US 20170278743 A1 (Tsai et al hereinafter Tsai) in view of US 20200105672 A1 (Madhavan et al hereinafter Madhavan).
Regarding claim 1, Tsai discloses a semiconductor device (the device of FIG. 2H ¶ [0005]), comprising: an interfacial layer (FIGS. 2A and 2H, ‘first layer’ of interfacial layer 206 which may be silicon oxide ¶ [0012, 0015-0016]) disposed over a channel region (FIGS. 2C and 2H, a channel region is formed between source/drain 218 when they are arranged in substrate 202 ¶ [0022]); a gate dielectric structure (FIGS. 2A and 2H, ‘second layer’/’dielectric portion’ of gate dielectric layer 206 and second gate dielectric layer 208 form a gate dielectric structure ¶ [0015-0016]) comprising: a first layer (FIGS. 2A and 2H, ‘second layer’/’dielectric portion’ of gate dielectric layer 206 over the ‘first layer’ of layer 206 may be a high-k metal oxide material, ¶ [0015]) of an oxide of a first metal over the interfacial layer, wherein the first layer has a first thickness (FIGS. 2A and 2H, ‘second layer’ of layer 206 has a level of thickness ¶ [0015]); and a second layer (FIGS. 2A and 2H, second gate dielectric layer 208 which may also be a high-k dielectric material ¶ [0016]) of an oxide or silicate of a second metal (second dielectric layer 208 is also formed of a high-k material, and Tsai taught that high-k materials were metal oxides ¶ [0015-0016]) disposed over the first layer (FIGS. 2A and 2H, second gate dielectric layer 208 is disposed over layer 206), wherein the second layer has second a thickness (FIGS. 2A and 2H, second gate dielectric layer 208 has a level of thickness); and a gate electrode (FIG. 2A and 2H, gate electrode 210 is disposed over second gate dielectric layer 208 ¶ [0012]) disposed over the gate dielectric structure.
Tsai does not explicitly disclose that the second thickness is at least three times greater than the first thickness, wherein an oxygen areal density of the oxide of the first metal is greater than an oxygen areal density of the oxide of the second metal.
Regarding the limitation “the second gate dielectric layer has a thickness that is at least three times greater than the first thickness”, Tsai discloses that layer 206 (part of which includes the first dielectric layer ¶ [0015]) and second dielectric layer 208 may each range in thickness of 5-30 Å (Tsai ¶ [0015-0016]), as well as that the thicknesses of layers 206 and 208 are important to adjust to avoid both leakage current and a short-channel effect (¶ [0015-0016]); the thicknesses of layers 206 and 208 therefore constituting result-effective variables.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thicknesses of both layers 206 and 208 as those thicknesses have been identified as result-effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a set of thicknesses wherein the second gate dielectric layer has a thickness that is at least three times greater than the first thickness, in order to balance the thicknesses to avoid both leakage current and a short-channel effect. In addition, while having the same suggested ranges of thicknesses, layer 208 is entirely a high-k dielectric, whereas layer 206 has both an interfacial sub-layer and a high-k sub-layer (Tsai ¶ [0015]); a person of ordinary skill in the art would therefore find a configuration wherein the high-k dielectric portion of layer 206 is at least three time less thick than the entirety of layer 208 an obvious option during the routine optimization. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding the limitation “an oxygen areal density of the first dielectric layer is greater than an oxygen areal density of the second dielectric layer”, Tsai does disclose that both hafnium oxide and zirconium oxide are suitable high-k materials for the dielectric layers. In addition, Madhavan further discloses a semiconductor device (FIG. 8A, structure 800 ¶ [0089]) wherein a gate dielectric layer (FIG. 8A, gate dielectric 806 ¶ [0089]) may be formed by an ALD process (¶ [0089]) and zirconium oxide, hafnium oxide, and lanthanum oxide are all considered interchangeable high-k materials for the gate dielectric layer (¶ [0098]). Further, the present application explicitly suggests that when the first metal is hafnium, the second metal may be lanthanum (present application ¶ [0070]), so using hafnium and lanthanum would provide an oxygen areal density relationship consistent with that of the claimed process.
Tsai and Madhavan both pertain to the field of forming gate dielectrics of semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to modify the device of Tsai in view of Madhavan such that the first metal is hafnium and the second metal is lanthanum, and consequently have an oxygen areal density of the first dielectric layer is greater than an oxygen areal density of the second dielectric layer, as a matter of obvious and interchangeable design choice when selecting the materials of the first and second dielectric layers, and in order to prevent leakage current while at the same time avoiding a short channel effect.
Regarding claim 2, Tsai in view of Madhavan discloses the limitations of claim 1 as detailed above and they further disclose that the interfacial layer comprises an oxide (the ‘first layer’ of first dielectric portion 206 may be silicon oxide, Tsai ¶ [0015]), and at least a portion of the first metal of the first layer is bonded to the interfacial layer (the ‘second layer’ of first dielectric portion 206 is disposed over the ‘first layer’ of first dielectric portion 206 without any intervening layers separating them, therefore at least of portion of them are bonded together ¶ [0015]; ¶ [0064] of the present application presents context for understanding the phrase ‘bonded to’).
Regarding claim 3, Tsai in view of Madhavan discloses the limitations of claim 1 as detailed above and they further disclose that at least a portion of the second metal is bonded to the first layer (Tsai FIGS. 2A and 2H, second dielectric portion 208 is disposed over the ‘second layer’ of first dielectric portion 206 without any intervening layers separating them therefore at least of portion of them are bonded together ¶ [0015-0016]; ¶ [0064] of the present application presents context for understanding the phrase ‘bonded to’).
Regarding claim 4, Tsai in view of Madhavan discloses the limitations of claim 1 as detailed above, but they do not explicitly teach that the first layer has a thickness less than 4 angstroms.
However, as has been discussed regarding claim 1, a cumulative thickness of the claimed first layer alongside the interfacial portion may be as low as 5 angstroms (Tsai ¶ [0015]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to select a thickness of less than 4 angstroms for the first layer when in the course of optimizing the thicknesses of the first and second layers as was described regarding claim 1 above, to balance thickness parameters to yield desirable properties such as preventing leakage current while at the same time avoiding a short channel effect.
Regarding claim 5, Tsai in view of Madhavan discloses the limitations of claim 1 as detailed above and they further disclose that the first metal is selected from aluminum, zinc, gallium, or hafnium (as detailed regarding claim 1 above, the first metal may be hafnium per Tsai ¶ [0015] and Madhavan ¶ [0089 and 0098]).
Regarding claim 6, Tsai in view of Madhavan discloses the limitations of claim 1 as detailed above and they further disclose that the second metal comprises hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, yttrium, or combinations thereof (as detailed regarding claim 1 above, the second metal may be lanthanum per Tsai ¶ [0015-0016] and Madhavan ¶ [0089 and 0098]).
Regarding claim 7, Tsai in view of Madhavan discloses the limitations of claim 1 as detailed above but they do not explicitly state that the gate dielectric structure has a capacitance equivalent thickness of 0.28 nm to 0.53 nm. However, the thicknesses of the two gate dielectric layers have already been identified as result-effective variables to balance the thicknesses to avoid both leakage current and a short-channel effect (Tsai ¶ [0015-0016]).
Since a person of ordinary skill in the art before the effective filing date of the claimed invention has been motivated to adjust the thicknesses of the first and second layers, the values of the first CET and second CET would also be adjusted since they are dependent on the first and second gate dielectric layers’ thicknesses. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary the capacitance equivalent thickness (CET) of the gate dielectric structure during the optimization of the thicknesses of the first and second gate dielectric layers of Tsai, and would have had a reasonable expectation of success to arrive at a capacitance equivalent thickness (CET) a range of 0.28 nm to 0.53 nm, in order to balance the thicknesses to avoid both leakage current and a short-channel effect (Tsai ¶ [0015-0016]).
Furthermore, the applicant has not presented persuasive evidence that the claimed CET is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Madhavan as applied to claim 1 above, and further in view of US patent publication US 20200135915 A1 (Savant et al hereinafter Savant).
Tsai in view of Madhavan discloses the limitations of claim 1 as detailed above, but did not state that interfacial layer has a thickness at least five times a thickness of the first layer, a consideration of the thickness of the interfacial layer portion with respect to the first layer’s thickness is not directly addressed by Tsai. Tsai does discuss that the first layer portion and the interfacial layer portion’s cumulative thickness may lie in the range of 5-30 angstroms (¶ [0015]), but does not compare the thicknesses of the ‘first layer’ and ‘interfacial layer’ portions of first gate dielectric layer 206 (FIGS. 2A and 2H). However, as was discussed regarding claim 1 above, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thicknesses of both layers 206 and 208 as those thicknesses have been identified as result-effective variables.
Further, one of ordinary skill in the art before the effective filing date of the claimed invention would have had a reasonable expectation of success to arrive at a configuration wherein the interfacial layer has a thickness at least five times a thickness of the first layer in view of Savant, who discloses a semiconductor device (the device of FIGS. 3A-3F, made by the process of FIG. 3G ¶ [0007]) wherein the range of suggested thicknesses for a silicon oxide interfacial layer includes 5-6nm, and the range of suggested thicknesses for a hafnium oxide gate dielectric includes 1nm, which correspond to materials taught by Tsai and satisfy the claim’s limitation. Accordingly, the person of ordinary skill in the art could have arrived at such a configuration when adjusting the thicknesses of the disclosed layers of Tsai when working to avoid both leakage current and a short-channel effect, as Savant has demonstrated such a disparity in thicknesses to be known in the art.
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness relationship is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai.
Tsai discloses a semiconductor device (the device of FIG. 2H ¶ [0005]), comprising: an interfacial layer (FIGS. 2A and 2H, ‘first layer’ of interfacial layer 206 ¶ [0012, 0015-0016]) disposed over a channel region (FIGS. 2C and 2H, a channel region is formed between source/drain 218 when they are arranged in substrate 202 ¶ [0022]), wherein the interfacial layer comprises an oxide of a semiconductor (‘first layer’ of interfacial layer 206 may be silicon oxide ¶ [0015]); a gate dielectric structure (FIGS. 2A and 2H, ‘second layer’/’dielectric portion’ of gate dielectric layer 206 and second gate dielectric layer 208 form a gate dielectric structure over the ‘first layer’ of gate dielectric layer 206 ¶ [0015-0016]) disposed over interfacial layer, wherein the gate dielectric structure has a first capacitance equivalent thickness (CET) (based on its material composition and thickness ‘second layer’/’dielectric portion’ of gate dielectric layer 206 and second gate dielectric layer 208 have a first CET) and comprises: a first layer (FIGS. 2A and 2H, ‘second layer’/’dielectric portion’ of gate dielectric layer 206 over the ‘first layer’ of layer 206 may be a high-k metal oxide material, ¶ [0015]) comprising one to three monolayers, wherein the one to three monolayers comprise an oxide of a first metal, wherein the first metal is selected from aluminum, zinc, gallium, or hafnium (‘second layer’/’dielectric portion’ of gate dielectric layer 206 may be hafnium oxide ¶ [0015]); and a second layer of an oxide or silicate of a second metal (FIGS. 2A and 2H, second dielectric layer 208 is also formed of a high-k material, and Tsai taught that high-k materials were metal oxides ¶ [0015-0016]) disposed over the first layer (FIGS. 2A and 2H, second gate dielectric layer 208 is disposed over layer 206), wherein the second layer has a second CET (based on its thickness and material composition second gate dielectric layer 208 has a second CET), wherein a difference between the first CET and the second CET is in a range from 0.04 nm to 0.29 nm; and a gate electrode (FIG. 2A and 2H, gate electrode 210 is disposed over second gate dielectric layer 208 ¶ [0012]) disposed over the gate dielectric structure.
Tsai does not explicitly state that the first layer comprises one to three monolayers, or that a difference between the first CET and the second CET is in a range from about 0.04 nm to about 0.29 nm. However, the thicknesses of the two gate dielectric layers have already been identified as result-effective variables to balance the thicknesses to avoid both leakage current and a short-channel effect (Tsai ¶ [0015-0016]).
Since a person of ordinary skill in the art before the effective filing date of the claimed invention has been motivated to adjust the thicknesses of the first and second layers, the number of monolayers in the first layer and the values of the first CET and second CET would also be adjusted since they are dependent on the first and second layers’ thicknesses. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary the number of monolayers in the first layer as well as the difference in a first capacitance equivalent thickness (CET) of the second dielectric layer and a second CET of a combined layer of the first layer and the second layer during the optimization of the thicknesses of the first and second layers of Tsai, and would have had a reasonable expectation of success to arrive at a first layer thickness that comprises one to three monolayers, wherein a difference in a first CET of a combined layer of the first and second layers and a second CET of the second layer is in a range from about 0.04 nm to about 0.29 nm, in order to balance the thicknesses to avoid both leakage current and a short-channel effect (Tsai ¶ [0015-0016]).
Furthermore, the applicant has not presented persuasive evidence that the number of first layer monolayers or the claimed CET is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai as applied to claim 9 above, and further in view of Madhavan.
Regarding claim 10, Tsai discloses the limitations of claim 9 as detailed above but does not explicitly disclose that the oxide of the first metal has an oxygen areal density greater than an oxygen areal density of the oxide of the second metal; Tsai does disclose that both hafnium oxide and zirconium oxide are suitable high-k materials for the dielectric layers. In addition, Madhavan further discloses a semiconductor device (FIG. 8A, structure 800 ¶ [0089]) wherein a gate dielectric layer (FIG. 8A, gate dielectric 806 ¶ [0089]) may be formed by an ALD process (¶ [0089]) and zirconium oxide, hafnium oxide, and lanthanum oxide are all considered interchangeable high-k materials for the gate dielectric layer (¶ [0098]). Further, the present application explicitly suggests that when the first metal is hafnium, the second metal may be lanthanum (present application ¶ [0070]), so using hafnium and lanthanum would provide an oxygen areal density relationship consistent with that of the claimed process.
Tsai and Madhavan both pertain to the field of forming gate dielectrics of semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to modify the device of Tsai in view of Madhavan such that the first metal is hafnium and the second metal is lanthanum, and consequently have an oxygen areal density of the first dielectric layer is greater than an oxygen areal density of the second dielectric layer, as a matter of obvious and interchangeable design choice when selecting the materials of the first and second dielectric layers, and in order to prevent leakage current while at the same time avoiding a short channel effect.
Regarding claim 11, Tsai in view of Madhavan discloses the limitations of claim 10 as detailed above, and Madhavan further discloses that the second metal comprises hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, yttrium, or combinations thereof (based on the modification of Tsai in view of Madhavan ¶ [0089 and 0098], the second metal may be lanthanum).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai as applied to claim 9 above, and further in view of Savant.
Tsai discloses the limitations of claim 9 as detailed above, but did not state that interfacial layer has a thickness at least five times greater than a thickness of the first layer, a consideration of the thickness of the interfacial layer portion with respect to the first layer’s thickness is not directly addressed by Tsai. Tsai does discuss that the first layer portion and the interfacial layer portion’s cumulative thickness may lie in the range of 5-30 angstroms (¶ [0015]), but does not compare the thicknesses of the ‘first layer’ and ‘interfacial layer’ portions of first gate dielectric layer 206 (FIGS. 2A and 2H). However, as was discussed regarding claim 9 above, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thicknesses of both layers 206 and 208 as those thicknesses have been identified as result-effective variables.
Further, one of ordinary skill in the art before the effective filing date of the claimed invention would have had a reasonable expectation of success to arrive at a configuration wherein the interfacial layer has a thickness at least five times greater than a thickness of the first layer in view of Savant, who discloses a semiconductor device (the device of FIGS. 3A-3F, made by the process of FIG. 3G ¶ [0007]) wherein the range of suggested thicknesses for a silicon oxide interfacial layer includes 5-6nm (¶ [0063]), and the range of suggested thicknesses for a hafnium oxide gate dielectric includes 1nm (¶ [0063]), which correspond to materials taught by Tsai and satisfy the claim’s limitation. Accordingly, the person of ordinary skill in the art could have arrived at such a configuration when adjusting the thicknesses of the disclosed layers of Tsai when working to avoid both leakage current and a short-channel effect, as Savant has demonstrated such a disparity in thicknesses to be known in the art.
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness relationship is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Claims 13-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over US patent publication US 20190109204 A1 (Cheng et al hereinafter Cheng) in view of Tsai.
Regarding claim 13, Cheng discloses a semiconductor device (FIGS. 2A-2B, device 100A ¶ [0006, 0023]), comprising: a semiconductor material (FIGS. 2A-2B, an upper layer of first semiconductor material 105 ¶ [0027]); a gate dielectric structure (FIGS. 2A-2B, high-k dielectric stack 121 ¶ [0028]) over and along sidewalls of the semiconductor material (FIG. 2B, high-k dielectric stack 121 is located over and along sidewalls of an upper layer of semiconductor 105), wherein the gate dielectric structure comprises: a first dielectric layer (FIG. 2B, high-k dielectric layer 122 may be hafnium oxide ¶ [0028]) being made of an oxide of a first metal; and a second dielectric layer (FIG. 2B, high-k dielectric layer 124 is located over layer 122 ¶ [0028]) over the first dielectric layer; and a gate electrode (FIG. 2B, conductive layer 126A, which is part of gate stack 107A, serves as a gate electrode and is located over ¶ [0028]) over the gate dielectric structure.
Cheng does not explicitly disclose that an oxygen areal density of the first dielectric layer is greater than an oxygen areal density of the second dielectric layer, and wherein the first dielectric layer is thinner than the second dielectric layer, comparisons of those parameters not being elements of particular importance to the disclosure of their invention. Cheng does teach that ranges of thicknesses for the first and second dielectric layer may overlap (¶ [0028]).
However, Tsai discloses a semiconductor device (the device of FIG. 2H ¶ [0005]), comprising: a first dielectric layer (FIGS. 2A and 2H, ‘second layer’/’dielectric portion’ of gate dielectric layer 206 which may be a high-k metal oxide material, ¶ [0015]) of an oxide of a first metal, wherein the first layer has a first thickness (FIGS. 2A and 2H, ‘second layer’ of layer 206 has a level of thickness ¶ [0015]); and a second dielectric layer (FIGS. 2A and 2H, second gate dielectric layer 208 which may also be a high-k dielectric material ¶ [0016]). Tsai also discloses that layer 206 (part of which includes the first dielectric layer ¶ [0015]) and second dielectric layer 208 may each range in thickness of 5-30 Å (Tsai ¶ [0015-0016]), as well as that the thicknesses of layers 206 and 208 are important to adjust to avoid both leakage current and a short-channel effect (¶ [0015-0016]); the thicknesses of the first and second dielectric layers therefore constituting result-effective variables; Cheng also notes that short channel control is a concern to be accounted for in the art (¶ [0003]).
It would therefore have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the thicknesses of both the first and second dielectric layers of Cheng as those thicknesses have been identified as result-effective variables. Further, one of ordinary skill in the art would have had a reasonable expectation of success to arrive at a set of thicknesses wherein the first dielectric layer is thinner than the second dielectric layer, to balance the thicknesses to avoid both leakage current and a short-channel effect. MPEP 2144.05.
Furthermore, the applicant has not presented persuasive evidence that the claimed thickness is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Cheng in view of Tsai do not explicitly disclose that an oxygen areal density of the first dielectric layer is greater than an oxygen areal density of the second dielectric layer.
Cheng does however suggest that hafnium oxide and lanthanum oxide are both suitable high-k materials which may be used in their first and second dielectric layers 122 and 124 respectively (Cheng ¶ [0028, 0060]). Further, the present application explicitly suggests that when the first metal is hafnium, the second metal may be lanthanum (present application ¶ [0070]), so using hafnium and lanthanum would provide an oxygen areal density relationship consistent with that of the claimed process.
Cheng and Tsai both pertain to the field of forming gate dielectrics of semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to modify the device of Cheng in view of Tsai further in view of Cheng such that the first metal is hafnium and the second metal is lanthanum, and consequently have an oxygen areal density of the first dielectric layer is greater than an oxygen areal density of the second dielectric layer, as a matter of obvious and interchangeable design choice when selecting the materials of the first and second dielectric layers, which may be found beneficial from consideration of materials costs and in order to prevent leakage current while at the same time avoiding a short channel effect.
Regarding claim 14, Cheng in view of Tsai discloses the limitations of claim 13 as detailed above, and they further disclose that the first metal is aluminum, zinc, gallium, or hafnium (Cheng ¶ [0028], the first metal in first dielectric layer 122 may be hafnium).
Regarding claim 15, Cheng in view of Tsai discloses the limitations of claim 13 as detailed above, and they further disclose that the second dielectric layer is made of an oxide of a second metal (in view of the modification of Cheng in view of Tsai, the second dielectric layer may be lanthanum oxide, Cheng ¶ [0060]).
Regarding claim 17, Cheng in view of Tsai discloses the limitations of claim 13 as detailed above, but they do not explicitly state that the gate dielectric structure has a first capacitance equivalent thickness (CET), the second dielectric layer has a second CET, wherein a difference between the first CET and the second CET is in a range from 0.04 nm to 0.29 nm.
However, the thicknesses of the two gate dielectric layers have been identified as result-effective variables to balance the thicknesses to avoid both leakage current and a short-channel effect (Tsai ¶ [0015-0016]).
Since a person of ordinary skill in the art before the effective filing date of the claimed invention has been motivated to adjust the thicknesses of the first and second dielectric layers, the values of the first CET and second CET would also be adjusted since they are dependent on the first and second dielectric layers’ thicknesses. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary the difference in a first capacitance equivalent thickness (CET) of a combined layer of the first dielectric layer and the second dielectric layer and a second CET of the second dielectric layer during the optimization of the thicknesses of the first and second dielectric layers, and would have had a reasonable expectation of success to arrive at a configuration wherein a difference between the first CET and the second CET is in a range from 0.04 nm to 0.29 nm, in order to balance the thicknesses to avoid both leakage current and a short-channel effect (Tsai ¶ [0015-0016]).
Furthermore, the applicant has not presented persuasive evidence that the claimed CET is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 18, Cheng in view of Tsai discloses the limitations of claim 13 as detailed above, and they further disclose an interfacial layer between the gate dielectric structure and the semiconductor material (Cheng FIG. 2B, interfacial layer 120 is between semiconductor layer 105 and high-k dielectric stack 121 ¶ [0028]).
Regarding claim 19, Cheng in view of Tsai discloses the limitations of claim 13 as detailed above, but did not state that the first dielectric layer is made of one to three monolayers of the oxide of the first metal.
However, the thicknesses of the two gate dielectric layers have been identified as result-effective variables to balance the thicknesses to avoid both leakage current and a short-channel effect (Tsai ¶ [0015-0016]).
Since a person of ordinary skill in the art before the effective filing date of the claimed invention has been motivated to adjust the thicknesses of the first and second dielectric layers, the number of monolayers used to form the oxide of the first metal (the high-k dielectric layer 121 may be formed by an ALD process, Cheng ¶ [0060]) would also be a result-effective variable on the same basis. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to vary the number of monolayers of the oxide of the first metal during the optimization of the thicknesses of the first and second layers of Tsai, and would have had a reasonable expectation of success to arrive at a first dielectric layer made of one to three monolayers of the oxide of the first metal, in order to balance the thicknesses to avoid both leakage current and a short-channel effect (Tsai ¶ [0015-0016]).
Furthermore, the applicant has not presented persuasive evidence that the number of first layer monolayers or the claimed CET is for a particular purpose that is critical to the overall claimed invention (i.e., that the invention would not work without the specific claimed dimensions).
Regarding claim 20, Cheng in view of Tsai discloses the limitations of claim 13 as detailed above, and they further disclose that a k-value of the second dielectric layer is greater than the first dielectric layer (present application explicitly suggests that when the first metal is hafnium, the second metal may be lanthanum in ¶ [0070], so using hafnium and lanthanum would provide a corresponding k-value relationship consistent with the claim’s limitation).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng in view of Tsai as applied to claim 13 above, and further in view of US patent publication US 20200105532 A1 (Liao et al hereinafter Liao).
Cheng in view of Tsai discloses the limitations of claim 13 as detailed above, but do not further disclose that the second dielectric layer is made of a silicate of a second metal.
However, Liao discloses a semiconductor device (the device of FIG. 15) wherein a high-k dielectric layer may be interchangeably formed of lanthanum oxide and lanthanum silicate (FIG. 15, dielectric layer 62, ¶ [0028]).
Cheng, Tsai, and Liao all pertain to the field of forming gate dielectrics of semiconductor devices, placing them in the same field of endeavor as the claimed invention. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would also have found it obvious to modify the device of Cheng in view of Tsai further in view of Liao by using lanthanum silicate in place of lanthanum oxide as the material for the second dielectric layer, as Liao has demonstrated the two materials to be known and interchangeable alternatives in the art, which a person of ordinary skill in the art may find beneficial from consideration of materials costs and changing market conditions.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US patent publications US 20190378911 A1, US 20190318967 A1 (notably FIG. 12 device 310 region, dielectrics 80, 82, 84) and US 20190140082 A1 (notably ¶ [0019-0024] layers 116, 118, and 120), US 20170200803 A1 (notably ¶ [0101]), and US patent US 10825736 B1 (notably FIG. 10, HK dielectric materials Col 6 lines 20-30, IL layer 42).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD RHETT CHEEK whose telephone number is (571)272-3461. The examiner can normally be reached Monday - Thursday 7:30am - 5pm, Every other Friday 8:30am - 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/E.R.C./Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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