DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
2. Claim 15 is objected to because of the following informalities: claim 15, line 4, recites: “the second side” which lacks an antecedent basis. For examination purposes, “the second side” is interpreted to be “a second side of the substrate”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
3. Claims 1-3 and 15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ganguly et al. U.S. Patent Application Publication 2021/0408246 A1 (the ‘246 reference).
Referring to claim 1, the ‘246 reference discloses a method of forming a semiconductor device, comprising:
forming a sacrificial layer (150, Fig. 1C, para [25] (paragraph(s) [0025])) in an opening of a substrate (102, comprising 103/104, see Fig. 1B, para [22]);
forming a first doped region (130, Fig. 1C, para [26]) in the opening over the sacrificial layer (150);
flipping the substrate (“flipped over”, para [31], see also Fig. 1E);
removing (“polished back”, para [32]) a portion of the substrate to expose the sacrificial layer (150); and
replacing the sacrificial layer (150) with a first contact (184, Fig. 1H, para [35]).
Referring to claim 2, the reference further discloses forming a gate electrode (162/163, Fig. 1D, para [27]) over the substrate (103/104) and a second doped region (130) in the substrate (103/104), wherein the first doped region (130) and the second doped region (130) are disposed at opposite sides of the gate electrode (130).
Referring to claim 3, the reference further discloses that the first and second doped regions (130) are source and drain regions (para [17, 26]).
Referring to claim 15 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a method of forming a semiconductor device, comprising:
forming a gate structure (162/163, Fig. 1D, para [27]) over a first side of a substrate (103/104, see also Fig. 1B) and a first source/drain region (130) and a second source/drain region (130, Fig. 1D) in the substrate (103/104, see also Figs. 1B-1C);
forming a dummy contact (150/142, Fig. 1D, para [25, 30]) in the substrate (103/104) between a second side of the substrate and the second source/drain region (130), wherein the dummy contact (150/142) is in direct contact with the second source/drain region (130); and
replacing the dummy contact (150/142) with a conductive via (184, Fig. 1H, para [35]).
Allowable Subject Matter
4. Claims 8-14 are allowable over the prior art of record.
Claims 4-7 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a method of forming a semiconductor device with all exclusive limitations as recited in claims 4-5, 7-8, 16-17 and 19-20, which may be characterized (claim 4) in, before flipping the substrate, forming a second contact on the substrate to electrically connect to the second doped region, and in forming a wiring structure over the substrate to electrically connect to the second doped region through the second contact, (claim 5) in, after exposing the sacrificial layer, removing portions of the liner and the dielectric layer to expose the sacrificial layer, (claim 7) in forming a wiring structure over the substrate and electrically connected to the first doped region through the first contact, (claim 8) forming first wirings and a first memory cell between the first wirings over a first side of the substrate, wherein the first wirings are electrically connected to the first source/drain region, and the first memory cell is electrically connected to the first wirings, and in forming second wirings and a second memory cell between the second wirings over a second side of the substrate, wherein the second wirings are electrically connected to the second source/drain region, and in that the second memory cell is electrically connected to the second wirings, (claim 16) in that the dummy contact is formed of an epitaxial material, and in that replacing the dummy contact with the conductive via comprises removing the epitaxial material to form an opening and filling a conductive material in the opening, (claim 17) in removing portions of the substrate from the second side to expose the dummy contact, in forming a first dielectric layer to cover the dummy contact, and in removing portions of the first dielectric layer by a planarization process to expose the dummy contact, (claim 19) in forming a wiring structure and a memory cell in the wiring structure over the second side to electrically connect the second source/drain region through the conductive via, and (claim 20) in forming a wiring structure and a memory cell over the first side of the substrate to electrically connect to the first source/drain region.
Conclusion
5. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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09-11-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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