Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 29, 2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Taiwan on February 26, 2024. It is noted, however, that applicant has not filed a certified copy of the TW113106855 application as required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Interposer Device with Alternating Communication Direction Signal Lines and Semiconductor Package Device Comprising the Same.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1, 7-9, 11, and 17-19 objected to because of the following informalities:
Claims 1 and 11 introduce “the transmission”, which does not have exact antecedent basis. The objection can be overcome by correcting the limitation to “transmission” or “a transmission”.
Claims 7-9 and 17-19 introduce “the uppermost one” and “the lowermost one”, which do not have exact antecedent basis. The objection can be overcome by correcting the limitations to “an uppermost one” and “a lowermost one” respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 recites the limitation "the width" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 3 recites the limitation "the spacing" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the width" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 13 recites the limitation "the spacing" in line 1. There is insufficient antecedent basis for this limitation in the claim.
For purposes of examination, the claims are interpreted by the Examiner as follows:
Claim 2: “…wherein a width in a third direction of each of the plurality of signal lines is lower than… plurality of ground lines, wherein the third direction is different from the first, second, and vertical directions.”
Claim 3: “…wherein a spacing in a third direction between each of the plurality of signal lines…equal to each other…wherein the third direction is different from the first, second, and vertical directions.”
Claim 12: “…wherein a width in a third direction of each of the plurality of signal lines is lower than… plurality of ground lines, wherein the third direction is different from the first, second, and vertical directions.”
Claim 13: “…wherein a spacing in a third direction between each of the plurality of signal lines…equal to each other…wherein the third direction is different from the first, second, and vertical directions.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-13, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 20230387031 A1), hereinafter referred to as Yang, in view of Xu et al. (US 20260150737 A1).
Regarding Claim 1, Yang teaches an interposer device ([0026] “an RDL structure 15”; FIG. 1: 15), configured to provide the transmission of a plurality of communication signals between two chips ([0023] “at least two dies are coupled to a redistribution layer (RDL) structure or an interposer”; FIG. 1, 2), wherein the interposer device comprises:
a plurality of circuit layers, electrically connected between the two chips and arranged along a vertical direction ([0046] “spreads out the eight signal lines in four RDL metal layers—RDL1, RDL2, RDL3, and RDL4”; FIG. 11, 12: RDL1-4), wherein each of the plurality of circuit layers is configured to take a first direction or a second direction as a signal transmission direction for transmitting the plurality of communication signals, wherein the first direction is opposite the second direction, and both the first direction and the second direction are different from the vertical direction ([0046] “four equally spaced signal lines 310”; a signal line is implied to be able transmit signals in both directions),
wherein each of the plurality of circuit layers comprises a plurality of signal lines and a plurality of ground lines arranged alternately ([0046] “This allows one ground line 320 to be horizontally inserted between two adjacent signal lines 310 in a given RDL metal layer.”; FIG. 12: 310, 320),
the projections of the signal lines in one of the plurality of circuit layers along the vertical direction on an adjacent one of the plurality of circuit layers overlap the plurality of ground lines in the adjacent one of the plurality of circuit layers ([0046] “Additionally, signal lines 310 in adjacent RDL metal layers are offset (not vertically aligned) such that signal lines in different RDL metal layers are also vertically spaced apart by one ground line 320.”; FIG. 12: 310, 320).
Yang does not teach three of the plurality of circuit layers sequentially arranged, the signal transmission direction of the first circuit layer is opposite to the signal transmission direction of the last circuit layer.
Xu teaches a set of pins arranged where two pins transmit opposite signals ([0107] “When the two control signal pins (the second pin 112 and the third pin 113) transmit a DQS differential clock signal, polarities of a differential signal pair during transmission are opposite”; FIG. 2: 112, 113), wherein crosstalk on a third pin equidistance from the first two is fully cancelled ([0107] “In this way, interference in two adjacent single-ended signal pins (a fifth pin 115 and a sixth pin 116) on an upper side and a lower side in a second direction Y can be fully canceled”)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the interposer device of Yang with the connection structure of Xu. The concept of using two opposing currents to mitigate magnetic interference in a third is well known in the art and documented. Applying this concept through alternating signal direction to Yang, which already has alternating ground lines to prevent crosstalk, would only further help the device deal with interference. Please refer to the annotated FIG. 2 below. Matching 112 to M1 of the claimed invention, 115 and 116 to M2, and 113 to M3 results in us getting the same structure as the claimed invention if we tile the pins down the line.
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Regarding Claim 2, Yang in view of Xu teaches the interposer device of claim 1. Yang further teaches a width in a third direction of each of the plurality of signal lines is lower than… plurality of ground lines, wherein the third direction is different from the first, second, and vertical directions (FIG. 12).
Regarding Claim 3, Yang in view of Xu teaches the interposer device of claim 1. Yang further teaches a spacing in a third direction between each of the plurality of signal lines…equal to each other…wherein the third direction is different from the first, second, and vertical directions (FIG. 12).
Regarding Claim 7, Yang in view of Xu teaches the interposer device of claim 1. Yang further teaches the plurality of circuit layers is an even number.
Yang does not teach the signal transmission direction of the uppermost one of the plurality of circuit layers is opposite to the signal transmission direction of an adjacent circuit layer, and the signal transmission direction of the lowermost one of the plurality of circuit layers is opposite to the signal transmission direction of another adjacent circuit layer.
However, the limitation of having opposite circuit layers amongst a sequence of three to have opposite signal directions leads two possible configurations: where the first two layers are the same direction, as well as the last two; or the first two layers are different direction, and as well for the last two.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to choose the configuration described in the claim for the interposer device of Yang in view of Xu, because a person of ordinary skill would have had good reason to pursue the known options of the two possible configurations which is considered to be within his or her technical grasp. This leads to the anticipated success of reducing crosstalk and it is determined that choosing the order of directional layers is not of innovation, but of ordinary skill and common sense. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding Claim 8, Yang in view of Xu teaches the interposer device of claim 1.
Yang does explicitly teach the number of the plurality of circuit layers to be an odd number. Yang also does not teach the signal transmission direction of the uppermost one of the plurality of circuit layers is opposite to the signal transmission direction of an adjacent circuit layer, and the signal transmission direction of the lowermost one of the plurality of circuit layers is same as the signal transmission direction of another adjacent circuit layer.
However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to simply add another layer of connections to the interposer device of Yang in view of Xu. Adding this layer does not change the function and overall structure of the device, and simply adds another set of connection points for the two chips to connect to each other with.
Additionally, similar to the reasoning in Claim 7, having an odd number of circuit layers in addition to the limitation from Claim 1 only results in two possible configurations: the top layer having the same direction as the adjacent layer, and the bottom having a different direction as the adjacent layer; and the top layer having a different direction versus the bottom having a same direction.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to choose the configuration described in the claim for the interposer device of Yang in view of Xu, because a person of ordinary skill would have had good reason to pursue the known options of the two possible configurations which is considered to be within his or her technical grasp. This leads to the anticipated success of reducing crosstalk and it is determined that choosing the order of directional layers is not of innovation, but of ordinary skill and common sense. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding Claim 9, Yang in view of Xu teaches the interposer device of claim 1.
Yang does explicitly teach the number of the plurality of circuit layers to be an odd number. Yang also does not teach the signal transmission direction of the uppermost one of the plurality of circuit layers is same as the signal transmission direction of an adjacent circuit layer, and the signal transmission direction of the lowermost one of the plurality of circuit layers is opposite to the signal transmission direction of another adjacent circuit layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add another layer of connections to the interposer device of Yang in view of Xu because of the reasoning described in claim 8.
Additionally, this claim makes use of the other configuration described in claim 8.
It would have been obvious to one of ordinary skill in the art to choose the other configuration because of the reasoning described in claim 8.
Regarding Claim 10, Yang in view of Xu teaches the interposer device of claim 1. Yang further teaches a plurality of dielectric layers, wherein the plurality of dielectric layers are disposed between the plurality of circuit layers and configured to shield the plurality of circuit layers ([0026] “the RDL structure 15 may be fabricated over front surfaces of the chip A and the chip B by depositing dielectric layers, forming openings in the dielectric layers, depositing a conductive material over the openings, and planarization.”).
Regarding Claim 11, Yang teaches a semiconductor package device ([0026] “semiconductor device package structure 10”; FIG. 1: 10), comprising:
a first chip ([0026] “chip A”; FIG. 1: A),
a second chip, configure to transmit a plurality of communication signals with the first chip through a plurality of channels ([0026] “chip B…disposed side-by-side over an RDL structure 15”; FIG. 1: B, 15, 16);
a package substrate ([0026] “The RDL structure 15 is then bonded to a substrate 12”; FIG. 1: 12); and
an interposer device ([0026] “an RDL structure 15”; FIG. 1: 15), electrically connected to the first chip, the second chip, the package substrate ([0023] “at least two dies are coupled to a redistribution layer (RDL) structure or an interposer”; FIG. 1, 2), and comprising a plurality of circuit layers, wherein the plurality of circuit layers are electrically connected between the first chip and the second chip to serve as the plurality of channels and are arranged along a vertical direction ([0046] “spreads out the eight signal lines in four RDL metal layers—RDL1, RDL2, RDL3, and RDL4”; FIG. 11, 12: RDL1-4), wherein each of the plurality of circuit layers is configured to take a first direction or a second direction as a signal transmission direction for transmitting the plurality of communication signals, wherein the first direction is opposite the second direction, and both the first direction and the second direction are different from the vertical direction ([0046] “four equally spaced signal lines 310”; a signal line is implied to be able transmit signals in both directions),
wherein each of the plurality of circuit layers comprises a plurality of signal lines and a plurality of ground lines arranged alternately ([0046] “This allows one ground line 320 to be horizontally inserted between two adjacent signal lines 310 in a given RDL metal layer.”; FIG. 12: 310, 320),
the projections of the signal lines in one of the plurality of circuit layers along the vertical direction on an adjacent one of the plurality of circuit layers overlap the plurality of ground lines in the adjacent one of the plurality of circuit layers ([0046] “Additionally, signal lines 310 in adjacent RDL metal layers are offset (not vertically aligned) such that signal lines in different RDL metal layers are also vertically spaced apart by one ground line 320.”; FIG. 12: 310, 320).
Yang does not teach three of the plurality of circuit layers sequentially arranged, the signal transmission direction of the first circuit layer is opposite to the signal transmission direction of the last circuit layer.
Xu teaches a set of pins arranged where two pins transmit opposite signals ([0107] “When the two control signal pins (the second pin 112 and the third pin 113) transmit a DQS differential clock signal, polarities of a differential signal pair during transmission are opposite”; FIG. 2: 112, 113), wherein crosstalk on a third pin equidistance from the first two is fully cancelled ([0107] “In this way, interference in two adjacent single-ended signal pins (a fifth pin 115 and a sixth pin 116) on an upper side and a lower side in a second direction Y can be fully canceled”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor package device of Yang with the connection structure of Xu because of the reasoning described in Claim 1.
Regarding Claim 12, Yang in view of Xu teaches the semiconductor package device of claim 11. Yang further teaches a width in a third direction of each of the plurality of signal lines is lower than… plurality of ground lines, wherein the third direction is different from the first, second, and vertical directions (FIG. 12).
Regarding Claim 13, Yang in view of Xu teaches the semiconductor package device of claim 11. Yang further teaches a spacing in a third direction between each of the plurality of signal lines…equal to each other…wherein the third direction is different from the first, second, and vertical directions (FIG. 12).
Regarding Claim 17, Yang in view of Xu teaches the semiconductor package device of claim 11. Yang further teaches the plurality of circuit layers is an even number.
Yang does not teach the signal transmission direction of the uppermost one of the plurality of circuit layers is opposite to the signal transmission direction of an adjacent circuit layer, and the signal transmission direction of the lowermost one of the plurality of circuit layers is opposite to the signal transmission direction of another adjacent circuit layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the signal directions in the way described because of the reasoning of claim 17.
Regarding Claim 18, Yang in view of Xu teaches the semiconductor package device of claim 11.
Yang does explicitly teach the number of the plurality of circuit layers to be an odd number. Yang also does not teach the signal transmission direction of the uppermost one of the plurality of circuit layers is opposite to the signal transmission direction of an adjacent circuit layer, and the signal transmission direction of the lowermost one of the plurality of circuit layers is same as the signal transmission direction of another adjacent circuit layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add another layer of connections to the interposer device of Yang in view of Xu, as well as to configure the signal directions in the way described because of the reasoning of claim 18.
Regarding Claim 19, Yang in view of Xu teaches the semiconductor package device of claim 11.
Yang does explicitly teach the number of the plurality of circuit layers to be an odd number. Yang also does not teach the signal transmission direction of the uppermost one of the plurality of circuit layers is same as the signal transmission direction of an adjacent circuit layer, and the signal transmission direction of the lowermost one of the plurality of circuit layers is opposite to the signal transmission direction of another adjacent circuit layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add another layer of connections to the interposer device of Yang in view of Xu, as well as to configure the signal directions in the way described because of the reasoning of claim 19.
Regarding Claim 20, Yang in view of Xu teaches the semiconductor package device of claim 11. Yang further teaches a plurality of dielectric layers, wherein the plurality of dielectric layers are disposed between the plurality of circuit layers and configured to shield the plurality of circuit layers ([0026] “the RDL structure 15 may be fabricated over front surfaces of the chip A and the chip B by depositing dielectric layers, forming openings in the dielectric layers, depositing a conductive material over the openings, and planarization.”).
Claims 4-5 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Xu as applied to claims 1 and 11 above, and further in view of Shih et al. (US 20160307852 A1), hereinafter referred to as Shih.
Regarding Claim 4, Yang in view of Xu teaches the interposer device of claim 1.
Yang does not teach a redistribution layer comprising a plurality of signal contacts and electrically connected to the two chips through a micro-bump.
Shih teaches a semiconductor package ([0013] “semiconductor package 100”; FIG. 1-5: 100) comprising a redistribution layer, wherein the redistribution layer is disposed above the plurality of circuit layers in the vertical direction ([0029] “a PPI structure 132 (sometimes also referred to as RDLs 132) is formed over die 200”; FIG. 2K: 132, 200) and comprises a plurality of signal contacts ([0028] “under bump metallurgies (UBMs) 128”; FIG. 2K: 128), and each of the plurality of signal contacts is configured to connect to an external device through a micro-bump ([0028] “External connectors 130 are formed over UBMs 128.”; FIG. 2K: 130, 128).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yang with the redistribution layer of Shih. Yang specifies a simple connection structure of contact vias (Yang [0026] “Each of the chip A and chip B is electrically coupled to the RDL structure 15 by way of contact vias 16.”), and one of ordinary skill can do a simple replacement with the redistribution layer of Shih to maintain the same level of connection.
Regarding Claim 5, Yang in view of Xu and Shih teaches the interposer device of claim 4.
Yang does not teach a plurality of vias, wherein the plurality of vias are buried between the redistribution layer and the plurality of circuit layers.
Shih teaches a plurality of conductive lines, wherein the plurality of vias are buried between the redistribution layer and the plurality of circuit layers, and are configured to electrically connect the plurality of signal contacts to the plurality of signal lines ([0028] “electrically connected to die 200 by conductive lines 104 and 106.”; FIG. 2K: 106).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yang with the redistribution layer of Shih because of the reasoning described in claim 4.
Regarding Claim 14, Yang in view of Xu teaches the semiconductor package device of claim 11.
Yang does not teach a redistribution layer comprising a plurality of signal contacts and electrically connected to the two chips through a micro-bump.
Shih teaches a semiconductor package ([0013] “semiconductor package 100”; FIG. 1-5: 100) comprising a redistribution layer, wherein the redistribution layer is disposed above the plurality of circuit layers in the vertical direction ([0029] “a PPI structure 132 (sometimes also referred to as RDLs 132) is formed over die 200”; FIG. 2K: 132, 200) and comprises a plurality of signal contacts ([0028] “under bump metallurgies (UBMs) 128”; FIG. 2K: 128), and each of the plurality of signal contacts is configured to connect to an external device through a micro-bump ([0028] “External connectors 130 are formed over UBMs 128.”; FIG. 2K: 130, 128).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yang with the redistribution layer of Shih because of the reasoning described in claim 4.
Regarding Claim 15, Yang in view of Xu and Shih teaches the semiconductor package device of claim 14.
Yang does not teach a plurality of vias, wherein the plurality of vias are buried between the redistribution layer and the plurality of circuit layers.
Shih teaches a plurality of conductive lines, wherein the plurality of vias are buried between the redistribution layer and the plurality of circuit layers, and are configured to electrically connect the plurality of signal contacts to the plurality of signal lines ([0028] “electrically connected to die 200 by conductive lines 104 and 106.”; FIG. 2K: 106).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Yang with the redistribution layer of Shih because of the reasoning described in claim 4.
Allowable Subject Matter
Claims 6 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Turner et al. (US 20230034619 A1), Ali et al. (US 20230245973 A1), and Zhang et al. (US 10580734 B2) are cited to teach anti-crosstalk structures, relevant to claims 1-20.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SHEN whose telephone number is (571)272-0642. The examiner can normally be reached M-Th 0730-1730.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW L SHEN/ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights