Prosecution Insights
Last updated: October 23, 2026
Application No. 18/786,617

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Non-Final OA §102§103§112
Filed
Jul 29, 2024
Priority
Dec 19, 2023 — CN 202311769048.4 +1 more
Examiner
CUTLER, ETHAN EDWARD
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fujian Jinhua Integrated Circuit Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
1y 2m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
61 granted / 66 resolved
+24.4% vs TC avg
Moderate +11% lift
Without
With
+11.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
18 currently pending
Career history
90
Total Applications
across all art units

Statute-Specific Performance

§103
61.5%
+21.5% vs TC avg
§102
27.4%
-12.6% vs TC avg
§112
11.1%
-28.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 66 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. It is suggested that the title include the phrase “including protrusions on a peripheral edge.” Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 10 recites the limitation “the first protrusion” in ln. 1-2. There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, it is assumed that this term is meant to recite “the plurality of protrusions.” Claim 10 recites the limitation “the second protrusion” in ln. 2. There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, it is assumed that this term is meant to recite “the plurality of protrusions.” To further clarify, the first and second protrusions of claim 10 are assumed to both be part of the plurality recited in claim 8 and are meant to draw antecedent basis from this term. Claim 10 recites the limitation “second edge” in ln. 4. There is insufficient antecedent basis for this limitation in the claim. In the interest of compact prosecution, it is assumed that this term is meant to recite “the second lateral surface.” Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 5, 7, and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Pat. Pub. No. US 20190172831 A1 to Chang et al. (hereinafter “Chang”). Regarding claim 1, Chang teaches a semiconductor device (figs. 1, 4, and 6), comprising: a substrate (301; fig. 6) [0030]; an extension pad array (region A excluding the serrated portion patterns 113, 115, 117, and 119; fig. 1) [0029] comprising a plurality of extension pads (openings 512; fig. 4) [0029] disposed on the substrate (301), the extension pads (512) being separately (having separation therebetween) arranged in a first direction (D1) and a second direction (D2); and a margin structure (region B including the serrated portions 113, 115, 117, and 119; fig. 1), disposed outside the extension pad array (A) and comprising a plurality of first protrusions (portion of region B between 113 and 115; fig. 1) [0025] and a plurality of second protrusions (portion of region B between 115 and 117; fig. 1) [0025] contacting respectively the first protrusions (between 113 and 115), wherein a side face (115a; fig. 1) of one of the first protrusions (between 113 and 115) and a side face (side 115; fig. 1) of one of the second protrusions (between 115 and 117) adjacent to each other define an acute angle (θ2, the angle being defined between 50 and 700 degrees; fig. 1) [0025] therebetween, and a portion (a single 120) of the extension pads (120) is disposed between the side face (115a) of the first protrusion and the side face (115) of the second protrusion. Regarding claim 5, Chang teaches the semiconductor device according to claim 1, wherein one of the first protrusions (113 to 115) directly contacts an adjacent one of the second protrusions (115 to 117), and is spaced apart from another adjacent one of the second protrusions (117 to 119; fig. 1). Regarding claim 7, Chang teaches the semiconductor device according to claim 1, further comprising: a dielectric layer (303 fig. 6) [0030], disposed on the substrate (301) and surrounding the margin structure (B including serrated edge structures) and the extension pads (120), wherein a portion of the dielectric layer (303) is sandwiched between each of the first protrusions (113 to 115, in region B, the dielectric layer being disposed in region B; figs. 1 & 6) and each of the second protrusions (115 to 117). Regarding claim 11, Chang teaches a method of fabricating a semiconductor device, comprising: providing a substrate (301; fig. 6) [0030]; forming an extension pad array (region A excluding the serrated portion patterns 113, 115, 117, and 119; fig. 1) [0029] on the substrate (301), the extension pad array (A) comprising a plurality of extension pads (openings 512; fig. 4) [0029] separately arranged in a first direction (D1) and a second direction (D2); and forming a margin structure (region B including the serrated portions 113, 115, 117, and 119; fig. 1) outside the extension pad array (A), the margin structure (B) comprising a plurality of first protrusions (portion of region B between 113 and 115; fig. 1) [0025] and a plurality of second protrusions (portion of region B between 115 and 117; fig. 1) [0025] respectively contacting each of the first protrusions (113 to 115), wherein a side face (115a; fig. 1) of one of the first protrusions (between 113 and 115) and a side face (side 115; fig. 1) of one of the second protrusions (between 115 and 117) adjacent to each other define an acute angle (θ2, the angle being defined between 50 and 700 degrees; fig. 1) [0025] therebetween, and a portion (a single 120) of the extension pads (120) is disposed between the side face (115a) of the first protrusion and the side face (115) of the second protrusion. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chang as applied to claim 5 above, and further in view of U.S. Pat. Pub. No. US 20100209825 A1 to Choi (hereinafter “Choi”). Regarding claim 6, Chang does not teach the semiconductor device according to claim 5, wherein a distance between the one of the first protrusions and the another adjacent one of the second protrusions is smaller than a length of one of the side face of the first protrusion and the side face of the second protrusion. Choi, however, teaches a semiconductor device (method for forming thereof; abstract) wherein a distance between the one of the first protrusions (one of spacers 17; fig. 5B) [0058] and the another adjacent one of the second protrusions (a separate spacer 17; fig. 5B) is smaller than a length of one of the side face (lateral side) of the first protrusion (one of 17) and the side face (lateral side) of the second protrusion (separate of 17). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Chang to comprise side face meeting the limitations of claim 6 to allow for device formation through spacer patterning tech as taught by Choi [0060]. Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of U.S. Pat. Pub. No. US 20180158827 A1 to You et al. (hereinafter “You”). Regarding claim 8, Chang teaches a semiconductor device, comprising: a substrate (300; fig. 6) [0030]; an extension pad array (region A excluding the serrated portion patterns 113, 115, 117, and 119; fig. 1) [0029], comprising a plurality of extension pads (openings 512; fig. 4) [0029] disposed on the substrate (300), the extension pads (512) being separately arranged in a first direction (D1) and in a second direction (D2); a margin structure (region B including the serrated portions 113, 115, 117, and 119; fig. 1), disposed outside the extension pad array (A) and comprising a plurality of protrusions (portion of region B between serrated portions; fig. 1) [0025], wherein each of the protrusions comprises a V-shaped recess (see fig. 1); and Chang does not teach a plurality of capacitors, respectively disposed on the V-shaped recess of each of the protrusions. Chang teaches that the embodiments may be used in a memory application but is not explicit in a description of a plurality of capacitors. You, however, teaches a semiconductor device (fig. 6A) with a plurality of capacitors (dummy capacitors DMC; fig. 6A) [0065] respectively disposed on the V-shaped recess (indents of the serrated edge design in fig. 6A) of each of the protrusions (portions of the structure not comprising RACs or DMCs forming indents in the pattern edge; fig. 6A). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention, to modify the semiconductor device of Chang to comprise a plurality of capacitors respectively disposed on the V-shaped recess of each of the protrusions to improve manufacturing margins as taught by You [0065]. Regarding claim 9, Chang in view of You teaches the semiconductor device according to claim 8, wherein each of the protrusions comprises a first protrusion (113 to 115) and a second protrusion (115 to 117) directly in contact with each other (physical contact), and the V-shaped recess (region of θ2) is disposed between the first protrusion (113 to 115) and the second protrusion (115 to 117). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of You as applied to claim 8 above, and further in view of Chinese Pat. Pub. No. CN 116723694 A to Tong et al. (hereinafter “Tong”). Regarding claim 10, Chang in view of You does not teach the semiconductor device according to claim 8, wherein the plurality of protrusions respectively comprises a first lateral surface and a second lateral surface, and a length of the first lateral surface is greater than a length of the second lateral surface (as below). Tong, however, teaches a semiconductor device wherein the plurality of protrusions (portions of dielectric layer 26 making up the first edge 24a and the second edge 24b; fig. 5) [n0030] respectively comprise a first lateral surface (as annotated below; fig. 5) and a second lateral surface (annotated below; fig. 5), and a length of the first lateral surface (as below) is greater than a length of the second lateral surface (as below). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Chang to comprise lateral surfaces satisfying the limitations of claim 10 to improve the stability and quality of the semiconductor memory as taught by Tong [n0008]. PNG media_image1.png 688 826 media_image1.png Greyscale Annotated fig. 5 from Tong Allowable Subject Matter Claims 2-4 and 12-18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 2 contains allowable subject matter because of its limitations considered together, and especially their interactivity. If the Applicant integrates this subject matter into the independent claims, it is suggested that the exact phrasing of claim 2 be included to assist in compact prosecution. The same suggestion is given for the allowable subject matter of claim 12 if it is integrated into independent claim 11. Claims 3-4 and 13-18 contain allowable subject matter by virtue of their dependence on an allowable claim. Regarding the allowable subject matter, it is noted that claim 2 (and claim 12) requires that each of the first and second protrusions respectively comprise first and second lateral surfaces (two for each protrusion) which are adjacent (i.e., adjoined to, next to) to the side face of the first protrusion and second protrusion. This particular limitation requires that the lateral surfaces be between the protrusions (thus satisfying the adjacent requirement). There is no reference found which cures the deficiencies of Chang in this matter. The closest references are: Tong, which teaches the relevant limitations except for the adjacent limitation (the lateral surfaces, P2, for example, are not adjacent to a first and second protrusion which make an acute angle, as required by claim 2; see fig. 5); CN 220108613 U to Yu-cheng Tong et al., which teaches the same limitations as above; and Choi, which teaches similar limitations (fig. 5B) but suffers from the same deficiencies concerning the term “adjacent.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN EDWARD CUTLER whose telephone number is (703)756-5415. The examiner can normally be reached Monday-Friday 7:30 am - 5:00 pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Richards can be reached on (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ETHAN EDWARD CUTLER/Examiner, Art Unit 2892 /NORMAN D RICHARDS/ Supervisory Patent Examiner, Art Unit 2892
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Prosecution Timeline

Jul 29, 2024
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+11.1%)
3y 5m (~1y 2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 66 resolved cases by this examiner. Grant probability derived from career allowance rate.

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