DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-18 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SON et al. 20110199804.
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Regarding claim 1, fig. 8 of Son discloses a device, comprising: stacking structures (stacking between EG2-EG7), wherein each of the stacking structures comprises alternately stacked first conductive lines 260 and first dielectric layers 250 (tunnel insulating layer and a blocking insulating layer - par [0065] and fig. 1M), and the first conductive lines has first sides and second sides opposite to the first sides; and
a plurality of second conductive lines (400 and 310) crossing over the first conductive lines, wherein widths of the second conductive lines are increased as the second conductive lines become far away from the first sides (see width 310 to width of 400).
Regarding claim 9, fig. 8 of SON discloses a device, comprising: stacking structures (stacking between EG2-EG7), wherein each of the stacking structures comprises alternately stacked first conductive lines 260 and first dielectric layers 250 (tunnel insulating layer and a blocking insulating layer), and the stacking structures are shaped into first staircase structures (left side) and second staircase structures (right side), respectively (see fig. 8); and
a plurality of second conductive lines (400 and 310) crossing over the first conductive lines and between the first staircase structures and second staircase structures, wherein widths of the second conductive lines are increased as the second conductive lines become far away from the first staircase structures (see width 310 to width of 400).
Regarding claim 16., fig. 8 of SON discloses a device, comprising:
stacking structures, wherein each of the stacking structures comprises alternately stacked first conductive lines and first dielectric layers (tunnel insulating layer and a blocking insulating layer);
a plurality of conductive contacts 350 electrically connected to first ends of the first conductive lines; and
a plurality of second conductive lines (400 and 310) over the first conductive lines, wherein widths of the second conductive lines are increased as the second conductive lines become far away from the conductive contacts (see width 310 to width of 400).
Regarding claim 2, fig. 8 of SON discloses further comprising a plurality of conductive contacts 350 electrically connected to the first conductive lines, wherein the conductive contacts are disposed at the first sides.
3. The device of claim 2, wherein the conductive contacts are electrically connected to active devices of a substrate disposed under the stacking structures.
Regarding claim 4, fig. 8 of SON discloses wherein the first conductive lines are extended along a first direction, and the second conductive lines are extended along a second direction substantially perpendicular to the first direction.
Regarding claim 5, fig. 8 of SON discloses wherein a plurality of spacings formed between the second conductive lines are decreased as the spacings become far away from the first sides (see spacing between 400 on the left and 400 on the right and compare that to spacing between 310).
Regarding claim 6, fig. 8 of SON discloses wherein a plurality of spacings formed between the second conductive lines are substantially the same (see spacing between 400a are substantially the same).
Regarding claim 7, fig. 5 of SON discloses further comprising memory material layers (a trap insulating layer) and channel layers 207, extending in between the stacking structures, and covering sidewalls of the stacking structures.
Regarding claim 8, fig. 8 of SON discloses further comprising conductive pillars (combination of 294/300), standing in between the stacking structures, and in lateral contact with the stacking structures through the memory material layers and the channel layers.
Regarding claim 10, fig. 8 of SON discloses further comprising a plurality of conductive contacts 350 electrically connected to the first conductive lines in the first staircase structures.
Regarding claim 11, SON discloses further comprising memory material layers 250 (trap insulating layer, a floating gate electrode) and channel layers, extending in between the stacking structures, and covering sidewalls of the stacking structures.
Regarding claim 12, fig. 5B of SON discloses further comprising first conductive pillars (pillars under 310s on one side) and second conductive pillars (pillars under 310s on one side), standing in between the stacking structures, and in lateral contact with the stacking structures through the memory material layers and the channel layers.
Regarding claim 13, fig. 5B of SON discloses wherein first ones of the second conductive lines are electrically connected to the first conductive pillars, and second ones of the second conductive lines are electrically connected to the second conductive pillars.
Regarding claim 14, fig. 5B of SON discloses wherein the first ones of the second conductive lines and the second ones of the second conductive lines are alternately arranged (alternate from one 310 to the next 310).
Regarding claim 15, SON discloses wherein the first conductive lines are word lines (par [0111]), and the second conductive lines are bit lines and source lines (310).
Regarding claim 17, fig. 8 of SON discloses wherein the stacking structures are shaped into first staircase structures and second staircase structures respectively, and the conductive contacts are disposed on the first staircase structures.
Regarding claim 18, figs. 6 and 8 of SON discloses wherein the second conductive lines are disposed over the stacking structures, and the conductive contacts are electrically connected to active devices (GSL – fig. 6) disposed under the stacking structures.
Regarding claim 20, fig. 8 of SON discloses further comprising memory material layers 207 (channel layer is a memory layer and channel form on and ON) and channel layers (207 between transistor channels), extending in between the stacking structures, and covering sidewalls of the stacking structures, wherein the memory material layers have bottom surfaces substantially coplanar with bottom surfaces of the first dielectric layers (layers of 10 which is insulator substrate (e.g., glass)) .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over SON.
Regarding claim 19, SON discloses the nearest one of the second conductive lines to the conductive contacts has a first width, the farthest one of the second conductive lines to the conductive contacts has a second width.
SON does not disclose a ratio of the second width to the first width is in a range of about 5 to about 20.
However, the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
As such it would have been obvious to form a device of SON a ratio of the second width to the first width is in a range of about 5 to about 20 in order to handle different current capacity per applicant design.
Conclusion
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893
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