DETAILED ACTION
Claim Objections
Claim 1 is objected to because of the recitation “the first-stage quantizer configured to receive the residual signal, and to apply a clock period delay to the residual signal” (lines 3-4) is not consistent with paragraph [0028] of the specification and/or the drawings. This recitation limitation should be amended to read as “the first-stage quantizer [102] comprising a passive integrator [201] configured to receive the residual signal [VRES(z)] and to apply a clock period delay [203] to the residual signal”. Clarification and/or correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,088,313. Although the claims at issue are not identical, they are not patentably distinct from each other because the conflicting claims are anticipated by the patented claims – claims are reproduced below for comparison.
Claim No.: __ of application 18/7876,686
Claim No.: __ of USP 12,088,313
1. An analog-to-digital converter comprising: a first-stage quantizer configured to receive an analog input signal and to generate a first-stage digital output signal based on the analog input signal and a residual signal based on the first-stage digital output signal and the analog input signal, the first-stage quantizer configured to receive the residual signal, and to apply a clock period delay to the residual signal, the analog-to-digital converter configured to determine a first-stage quantization error based on the residual signal.
1. An analog-to-digital converter comprising: a first-stage quantizer configured to receive an analog input signal and to generate a first-stage digital output signal based on the analog input signal and a residual signal based on the first-stage digital output signal and the analog input signal, the first-stage quantizer comprising a passive integrator configured to receive the residual signal, to apply a clock period delay to the residual signal, and to generate a passive integrator output signal, the analog-to-digital converter configured to determine a first-stage quantization error based on the residual signal and to generate a second-stage input signal based on the first-stage quantization error; a second-stage quantizer coupled to the first-stage quantizer, the second-stage quantizer configured to receive the second-stage input signal, to digitize the first-stage quantization error, and to generate a second-stage digital output signal based on the digitized first-stage quantization error; and a noise-cancellation filter coupled to the first-stage quantizer and the second-stage quantizer, the noise-cancellation filter configured to receive the first-stage digital output signal and the second-stage digital output signal and to generate a noise-cancellation output signal based on the first-stage digital output signal and the second-stage digital output signal, the noise-cancellation output signal comprising a quantization error component that is less than the first-stage quantization error.
2. The analog-to-digital converter of claim 1, wherein the analog-to-digital converter is further configured generate a second-stage input signal based on the first-stage quantization error, and the analog-to-digital converter further comprises: a second-stage quantizer coupled to the first-stage quantizer, the second-stage quantizer configured to receive the second-stage input signal, to digitize the first-stage quantization error, and to generate a second-stage digital output signal based on the digitized first-stage quantization error; and a noise-cancellation filter coupled to the first-stage quantizer and the second-stage quantizer, the noise-cancellation filter configured to receive the first-stage digital output signal and the second-stage digital output signal and to generate a noise-cancellation output signal based on the first-stage digital output signal and the second-stage digital output signal, the noise-cancellation output signal comprising a quantization error component that is less than the first-stage quantization error, wherein the quantization error component of the noise-cancellation filter is less than a second-stage quantization error.
1. “…to generate a second-stage input signal based on the first-stage quantization error; a second-stage quantizer coupled to the first-stage quantizer, the second-stage quantizer configured to receive the second-stage input signal, to digitize the first-stage quantization error, and to generate a second-stage digital output signal based on the digitized first-stage quantization error; and a noise-cancellation filter coupled to the first-stage quantizer and the second-stage quantizer, the noise-cancellation filter configured to receive the first-stage digital output signal and the second-stage digital output signal and to generate a noise-cancellation output signal based on the first-stage digital output signal and the second-stage digital output signal, the noise- cancellation output signal comprising a quantization error component that is less than the first- stage quantization error.”
3. The analog-to-digital converter of claim 2, wherein the second-stage digital output signal comprises a first component proportional to a negative value of the first-stage quantization error.
3. The analog-to-digital converter of claim 1, wherein the second-stage digital output signal comprises a first component proportional to a negative value of the first-stage quantization error.
4. The analog-to-digital converter of claim 3, wherein the first component of the second-stage digital output signal further comprises a second-stage signal transfer function.
4. The analog-to-digital converter of claim 3, wherein the first component of the second-stage digital output signal further comprises a second-stage signal transfer function.
5. The analog-to-digital converter of claim 4, wherein the second-stage signal transfer function is a constant.
5. The analog-to-digital converter of claim 4, wherein the second-stage signal transfer function is a constant.
6. The analog-to-digital converter of claim 3, wherein the second-stage digital output signal further comprises a second component including a second-stage quantization error.
6. The analog-to-digital converter of claim 3, wherein the second-stage digital output signal further comprises a second component including a second-stage quantization error.
7. The analog-to-digital converter of claim 1, wherein the first-stage quantizer comprises a passive integrator, the passive integrator includes a passive integrator gain factor and a clock period delay component configured to be applied to the residual signal.
11. The analog-to-digital converter of claim 1, wherein the passive integrator includes a passive integrator gain factor and a clock period delay component configured to be applied to the residual signal.
8. The analog-to-digital converter of claim 1, wherein the first-stage quantizer comprises a passive integrator, the passive integrator comprises a plurality of switches and a plurality of capacitors.
7. The analog-to-digital converter of claim 1, wherein the passive integrator comprises a plurality of switches and a plurality of capacitors.
9. The analog-to-digital converter of claim 2, wherein the noise-cancellation filter is further configured to apply a noise-cancellation noise transfer function to the second-stage digital output signal.
8. The analog-to-digital converter of claim 1, wherein the noise-cancellation filter is further configured to apply a noise-cancellation noise transfer function to the second-stage digital output signal.
10. The analog-to-digital converter of claim 9, wherein the first-stage quantizer is further configured to apply a first-stage noise transfer function to the first-stage quantization error.
9. The analog-to-digital converter of claim 8, wherein the first-stage quantizer is further configured to apply a first-stage noise transfer function to the first-stage quantization error.
11. The analog-to-digital converter of claim 10, wherein the noise-cancellation noise transfer function and the first-stage noise transfer function are the same functions.
10. The analog-to-digital converter of claim 9, wherein the noise-cancellation noise transfer function and the first-stage noise transfer function are the same functions.
12. A method of reducing a quantization error of an analog-to-digital converter comprising: receiving a residual signal, applying a clock period delay to the residual signal; determining a first-stage quantization error based on the residual signal; generating a digital output signal based on the first-stage quantization error; and generating a noise-cancellation output signal comprising a quantization error component from a quantizer that is less than the first-stage quantization error.
12. A method of reducing a quantization error of an analog-to-digital converter comprising: receiving an analog input signal; generating a first-stage digital output signal based on the analog input signal; generating a residual signal based on the analog input signal and the first-stage digital output signal; receiving the residual signal, applying a clock period delay to the residual signal, and generating a passive integrator output signal; determining a first-stage quantization error based on the residual signal; generating a second-stage digital output signal based on the first-stage quantization error; receiving the first-stage digital output signal and the second-stage digital output signal; and generating a noise-cancellation output signal comprising a quantization error component from a second-stage quantizer that is less than the first-stage quantization error.
13. The method of claim 12, further comprising applying a first-stage noise transfer function to the first-stage quantization error.
13. The method of claim 12, further comprising applying a first-stage noise transfer function to the first-stage quantization error.
14. The method of claim 13, further comprising applying a second-stage noise transfer function to a second-stage quantization error.
14. The method of claim 13, further comprising applying a second-stage noise transfer function to a second-stage quantization error.
15. The method of claim 14, further comprising applying a noise-cancellation noise transfer function to the digital output signal.
15. The method of claim 14, further comprising applying a noise-cancellation noise transfer function to the second-stage digital output signal.
16. The method of claim 15, wherein the noise-cancellation noise transfer function and the first-stage noise transfer function are the same functions.
16. The method of claim 15, wherein the noise-cancellation noise transfer function and the first-stage noise transfer function are the same functions.
17. The method of claim 12, wherein the digital output signal comprises a first component proportional to an inverted first-stage quantization error.
17. The method of claim 12, wherein the second-stage digital output signal comprises a first component proportional to an inverted first-stage quantization error.
18. The method of claim 12, further comprising applying a passive integrator gain factor and a clock period delay component to the residual signal.
18. The method of claim 12, further comprising applying a passive integrator gain factor and a clock period delay component to the residual signal.
19. A method of reducing a quantization error comprising: applying a clock period delay to a residual signal; extracting a first-stage quantization error from the residual signal; applying an inter-stage gain to an inverted form of the first-stage quantization error; and generating a noise cancellation output signal containing a quantization error component from a quantizer that is less than the first-stage quantization error.
19. A method of reducing a quantization error comprising: receiving a residual signal including a first-stage quantization error; applying a clock period delay to the residual signal and generating a passive integrator output signal; extracting the first-stage quantization error from the residual signal; applying an inter-stage gain to an inverted form of the first-stage quantization error; generating a second-stage digital output signal based on the inverted first-stage quantization error and the inter-stage gain; combining the second-stage digital output signal with a first-stage digital output signal; and generating a noise cancellation output signal based on the first-stage digital output signal and the second-stage digital output signal, the noise cancellation output signal containing a quantization error component from a second-stage quantizer that is less than the first-stage quantization error.
20. The method of claim 19, further comprising: generating a digital output signal based on the inverted first-stage quantization error and the inter-stage gain; and applying a noise cancellation noise transfer function to the digital output signal.
19. “generating a … digital output signal based on the inverted first-stage quantization error and the inter-stage gain; combining the second-stage digital output signal with a first-stage digital output signal; and generating a noise cancellation output signal based on the first-stage digital output signal and the second-stage digital output signal”.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845
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