DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statements filed on October 15, 2024 and July 29, 2024 have all been considered and made of record (note the attached copies of form PTO-1449).
Drawings
Fourty-four (44) sheets of drawings were filed on October 15, 2024 and have been accepted by the examiner.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 4, and 7-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,222,545 B2. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 at least disclose or suggest all of the limitations of claims 1-2, 4, and 7-9 of the present application.
Regarding claim 1; see claim 1 of U.S. Patent No. 12,222,545 B2. The second opening of claim 1 of U.S. Patent No. 12,222,545 B2 corresponds to the first opening of claim 1 of the present application.
Regarding claim 2; see claim 1 of U.S. Patent No. 12,222,545 B2. The first opening of claim 1 of U.S. Patent No. 12,222,545 B2 corresponds to the second opening of the present application.
Regarding claim 4; see claim 8 of U.S. Patent No. 12,222,545 B2.
Regarding claim 7; see claim 4 of U.S. Patent No. 12,222,545 B2.
Regarding claim 8; see claim 5 of U.S. Patent No. 12,222,545 B2.
Regarding claim 9; see claim 6 of U.S. Patent No. 12,222,545 B2.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-9, 15 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhang et al. (US 2021/0132309 A1), hereafter Zhang.
Regarding claims 1 and 7-9; Zhang discloses a method (see Figures 2A-2N, 3A and 4) comprising:
attaching a photonic integrated circuit die (integrated photonics chip 101; see figures 2B and 2C) to a carrier substrate (package substrate 102A), the photonic integrated circuit die (101) comprising an optical coupler (optical coupling devices 111 or 111A) and an insulating layer (integrated photonics chip 101 includes optical waveguides and integrated couplers, 111 or 111A, which are understood to be formed with lower cladding, core, and upper cladding layers, wherein the upper cladding layer are understood to be insulative, in addition lower portion of 102B forms an insulating layer; see paragraph 59; dielectric material, glass-reinformed epoxy laminate material, etc.) covering the optical coupler (111);
forming an encapsulant (102B; the upper and side portions of 102B encapsulate the photonic die 101) over the carrier substrate (102A) and the photonic integrated circuit die (101), the encapsulant (102B) extending along a sidewall of the photonic integrated circuit die (101; see Figure 2D);
forming a first redistribution structure (layer 102C includes contact pads 103, electrical vias 104B, and contact pads 106, thereby forming a redistribution structure; see Figure 2G) over the photonic integrated circuit die (101) and the encapsulant (102B); and
patterning the first redistribution structure to form a first opening (110; see Figure 2H) in the first redistribution structure, the opening extending through the insulating layer (lower layer portion of 102B) to expose exposing the optical coupler (111);
further comprising coupling an optical fiber (113) to the optical coupler (111 or alternatively 111A; see Figures 2N or alternatively 3A);
wherein the optical coupler (111A) is an edge coupler (see Figure 3A);
wherein the optical coupler (111) is a grating coupler (see Figure 2N; see paragraphs 56 and 100).
Regarding claims 15 and 19; Zhang discloses a method of forming a semiconductor device (see Figures 2A-2N, 3A), the method comprising:
depositing an molding compound (102B) over and around a photonic integrated circuit die (101), the photonic integrated circuit die (101) comprising an optical coupler (111, 111A) and an insulating layer (integrated photonics chip 101 includes optical waveguides and integrated couplers, 111 or 111A, which are understood to be formed with lower cladding, core, and upper cladding layers, wherein the upper cladding layer are understood to be insulative, in addition lower portion of 102B forms an insulating layer; see paragraph 59; dielectric material, glass-reinformed epoxy laminate material, etc.);
forming a redistribution structure (layer 102C includes contact pads 103, electrical vias 104B, and contact pads 106, thereby forming a redistribution structure; see Figure 2G) over the molding compound (102B), wherein forming the redistribution structure comprises forming a first dielectric layer (102C) over the molding compound (102B) and the photonic integrated circuit die (101), the first dielectric layer (102C) extending along sidewalls of the insulating layer (layer 102C extends along a top of the sidewalls of 102B which forms an insulating layer over die 101 and along a length of layers of 101, including cladding layers of any waveguide and optical coupling components therein);
forming a first opening (110) through the first dielectric layer (102C) and overlapping the optical coupler (111, 111A); and
performing an singulation process through the first opening (see paragraph 74);
wherein the photonic integrated circuit die (101) comprises a die connector (118) in the insulating layer, and wherein forming the redistribution structure (102, 104, 106) comprises forming a first metallization pattern extending through the first dielectric layer (102C) and electrically connected to the die connector (118).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2021/0132309 A1), hereafter Zhang.
Regarding claim 20; Zhang teaches that singulation is performed and may expose edge connectors (see Figure 3A, 5A and paragraph 87; singulation exposes edge connectors), but does not explicitly teach that the singulation process is further performed through the photonic integrated circuit die. Before the effective filing date of the present application, a person ordinary skill in the art would have found it obvious to use the singulation process to expose edge connectors of a desired length and to provide packages of a desired size to ensure optimal optical coupling and positioning with respect to other elements for an intended use, as no novel or unexpected advantages would appear to arise from singulation through the photonic chip die, which is a known method step for manufacturing packages in the art.
Allowable Subject Matter
Claims 2-6 and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if any double patenting rejections set for the above are overcome.
Claims 10-14 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, which is the most relevant prior art known, does not disclose or render obvious:
The method defined by claim 2, comprising: prior to forming the first redistribution structure, forming a second opening in the insulating layer to expose the optical coupler in combination with all of the limitations of base claim 1; or
A method of forming a semiconductor device, as defined by claim 10, the method comprising:
depositing a molding compound over and around a photonic integrated circuit die, the photonic integrated circuit die comprising an optical coupler, an insulating layer over the optical coupler, and a sacrificial layer over the insulating layer, the sacrificial layer covering the optical coupler;
planarizing the molding compound and at least upper portions of the sacrificial layer to expose the photonic integrated circuit die;
forming a redistribution structure over the molding compound, wherein forming the redistribution structure comprises forming a first dielectric layer over the molding compound and the photonic integrated circuit die, the first dielectric layer extending along sidewalls of the insulating layer; and
forming a first opening through the first dielectric layer and overlapping the optical coupler; or
The method defined by claim 16, wherein the photonic integrated circuit die further comprises a sacrificial layer over and along a sidewall of the first insulating layer, the sacrificial layer overlapping the optical coupler, wherein the method further comprises removing the sacrificial layer to define a second opening in the insulating layer in combination with all of the limitations of base claim 15.
Claims 3-6 are allowable by virtue of dependency from claim 2.
Claims 11-14 are allowable by virtue of dependency form claim 10.
Claims 17 and 18 are allowable by virtue of dependency from claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE R CONNELLY whose telephone number is (571)272-2345. The examiner can normally be reached Monday-Friday, 9 AM to 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHELLE R CONNELLY/Primary Examiner, Art Unit 2874
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