DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 07/01/2026 in which claims 1, 5, 10, 18 are amended has been entered of record.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As required by MPEP 2163(II)(A), when applicant adds new limitation, applicant must point out where support can be found. New limitations added to claims 1 and 10 requires “each extra plate of the multiple extra plates is not directly coupled to a memory cell”. Examiner unable to find the support for the new limitations in applicant’s specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kuroda (US Pat. 5,524,093) in view of Doumae et al. (US Pub. 2010/0020589).
Regarding claims 1, 10, and 18, Fig. 4 of Kuroda discloses an electronic device, comprising:
multiple plates [P11, P12, P31, P32], and respective multiple extra plates [P21, P22, P41, P42] each being an extra plate layer positioned near a plate of the multiple plates [P11, P12, P31, P32];
multiple plate groups [group of P11 & P12 and group of P31 and P32] each including a plate of the multiple plates [P11&P12, and P31&P32], a respective extra plate [P21 & P22 and P41 & P42] of the respective multiple extra plates, a memory cell group [SBL1, SBL2] including memory cells coupled to the plate, and a digit line group including digit lines [D1 to D8] coupled to respective memory cells of the memory cell group;
multiple driver pairs [as shows in Fig. 2, each plate is drives by plate driver PL-DV within PL-DEC] each including a plate driver and an extra plate driver respectively coupled to the plate and the extra plate of a plate group of the multiple plate groups, the plate driver configured to generate a plate signal [signal generates by the transistor pair shows in PL-DV] to be applied to the plate, the extra plate driver [since the extra plate also connects to the driver, the driver also generates signal applies to the extra plate] configured to generate an extra plate signal to be applied to the extra plate.
Kuroda discloses all claimed invention, but does not specifically disclose wherein each extra plate of the multiple extra plates is not directly coupled to a memory cell. However, Fig. 2 of Doumae discloses a memory device having multiple plates [PL0 to PLn] and respective multiple extra plates [DPL1 and DPL2] each being an extra plate layer positioned near a plate of the multiple plates [“near” is a relative term. Since applicant does not clearly define how near, DPL1 and DPL2 are considered being near PL0 to PLn], multiple plate groups [each PL0 to PLn, can be a group, or two of the plate lines can be a group] each including a plate of the multiple plates, a respective extra plate of the respective multiple extra plates [each extra plate DPL1 and DPL2 are corresponding to the regular plate lines (PL0 to PLn)], and extra plate driver [26, Dummy Plate Line Driver Circuit] respectively coupled the extra plate, and wherein each extra plate of the multiple extra plates [DPL1 and DPL2] is not directly coupled to a memory cell [DPL1 and DPL2 are not directly coupled to memory cell C0 to Cn].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Doumae’s extra plate line to the teachings of Kuroda’s memory having extra plate line such that Kuroda extra plate line is not directly coupled to a memory cell in a manner according to Doumae’s teachings for the purpose of fine-tuning a reference signal [paragraph 0012].
Regarding claims 2, 11, and 19, Fig. 2 of Kuroda discloses wherein the memory cells comprise ferroelectric memory cells [Q1 to Q10].
Regarding claim 3, Fig. 2 of Kuroda discloses a memory controller [PL-DEC] configured to select a plate of the multiple plates [P11 TO P31] and to control a memory cell access operation in the plate group of the selected plate.
Regarding claim 4, Fig. 2 of Kuroda discloses wherein the memory controller [PL-DEC] comprises a plate controller configured to control the generation of the plate signal [PL1 to PL3] and the extra plate signal [can be the same as PL1 to PL3] to be applied to the plate-extra plate pair including the selected plate for the memory cell access operation.
Regarding claims 5, Fig. 2 of Kuroda discloses wherein the plate controller [PL-DEC] is configured to control the generation of the extra plate signal for reducing crosstalk between the selected plate and one or more unselected plate of the multiple plates when the plate signal changes during a portion of the memory cell access operation [since PL-DEC generates signals to select or unselect a plate and extra plate, it inherently reduces cross talk between the selected plate].
Regarding claim 6, Fig. 2 of Kuroda discloses wherein the plate controller is configured to control the generation of the plate signal and the extra plate signal such that the plate signal and the extra plate signal are complementary signals during the portion of the memory cell access operation [since P11 & P21 are not active high at the same time. When P11 is high, P21 is off. Therefore, they are complementary signals].
Regarding claim 7, Fig. 23 of Kuroda discloses sense amplifier groups [SA, within RWC-1] respectively coupled to the multiple plate groups, the sense amplifier groups each including sense amplifiers [SA] selectively coupled to memory cells of the respective plate group through digit lines [D1 to D8] of the respective plate group.
Regarding claim 8 and 15, Fig. 12 of Kuroda discloses wherein the memory cell access operation is a sensing operation including a sensing phase [READ CYCLE] and a precharge phase [PRECHARGE], and the plate controller is configured to control the generation of the plate signal and the generation of the extra plate signal [PL1, PL2] such that the plate signal falls, and the extra plate signal rises, at a beginning of the precharge phase [clearly shows in Fig. 12].
Regarding claims 9 and 16, Fig. 12 of Kuroda discloses wherein the memory cell access operation is a sensing operation including a sensing phase [READ CYCLE] and a precharge phase [PRECHARGE], and the plate controller is configured to control the generation of the plate signal and the generation of the extra plate signal such that the plate signal rises, and the extra plate signal falls, at a beginning of the precharge phase [as shows in Fig. 12, precharge operation are corresponding to plate lines PL1 and PL2].
Regarding claims 12 and 20, Fig. 2 of Kuroda discloses wherein performing the memory cell access operation comprises: selecting a plate from the multiple plates [selected by PL-DEC]; and accessing a memory cell in the plate group including the selected plate, and applying the extra plate signal [PL1 to PL3] to the extra plate comprises reducing crosstalk between the selected plate and on or more unselected plates of the multiple plates by controlling the application of the extra plate signal to the extra plate positioned near the selected plate, the crosstalk caused by the application of the plate signal to the selected plate [since PL-DEC generates signals to select or unselect a plate and extra plate, it inherently reduces cross talk between the selected plate].
Regarding claim 13, Fig. 13 of Kuroda discloses controlling the application of the plate signal and the application of the extra plate signal such that the plate signal and the extra plate signal change simultaneously during a portion of the memory cell access operation [during PRECHARGE cycle, P11 and P22 change simultaneously to maintain signal at 0].
Regarding claim 14, Fig. 13 of Kuroda discloses wherein controlling the application of the plate signal and the application of the extra plate signal comprise controlling the application of the plate signal and the application of the extra plate signal such that the plate signal and the extra plate signal are complementary signals during the portion of the memory cell access operation [during WRITE CYCLE, P11 stay at 0, but P21 at vo/2].
Regarding claim 17, Fig. 13 of Kuroda discloses generating the plate signal [P11] and the extra plate signal [P21] to be applied to the selected plate and the extra plated positioned near the selected plate, respectively, such that the plate signal rises, and the extra plate signal falls, at a beginning of the precharge phase [at beginning of PRECHARGE, P21 falls to 0].
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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