DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
IDS filed on 09/05/2025 is fully considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kuroda (US Pat. 5,524,093).
Regarding claims 1, 10, and 18, Fig. 4 of Kuroda discloses an electronic device, comprising:
multiple plates [P11, P12, P31, P32];
multiple plate groups [group of P11 & P12 and group of P31 and P32] each including a plate of the multiple plates [P11&P12, and P31&P32], a memory cell group [SBL1, SBL2] including memory cells coupled to the plate, and a digit line group including digit lines [D1 to D8] coupled to respective memory cells of the memory cell group;
multiple plate-extra plate pairs [P21 & P22, P41 & P42] each including a respective plate of the multiple plates and an extra plate positioned near the respective plate of the multiple plates [P21 near P11, P22 near P12, P41 near P31, P42 near P32]; and
multiple driver pairs [as shows in Fig. 2, each plate is drives by plate driver PL-DV within PL-DEC] each including a plate driver and an extra plate driver respectively coupled to the plate and the extra plate of a plate-extra plate pair of the multiple plate-extra plate pairs [each plate is connects to a driver], the plate driver configured to generate a plate signal [signal generates by the transistor pair shows in PL-DV] to be applied to the plate, the extra plate driver [since the extra plate also connects to the driver, the driver also generates signal applies to the extra plate] configured to generate an extra plate signal to be applied to the extra plate.
Regarding claims 2, 11, and 19, Fig. 2 of Kuroda discloses wherein the memory cells comprise ferroelectric memory cells [Q1 to Q10].
Regarding claim 3, Fig. 2 of Kuroda discloses a memory controller [PL-DEC] configured to select a plate of the multiple plates [P11 TO P31] and to control a memory cell access operation in the plate group of the selected plate.
Regarding claim 4, Fig. 2 of Kuroda discloses wherein the memory controller [PL-DEC] comprises a plate controller configured to control the generation of the plate signal [PL1 to PL3] and the extra plate signal [can be the same as PL1 to PL3] to be applied to the plate-extra plate pair including the selected plate for the memory cell access operation.
Regarding claims 5, Fig. 2 of Kuroda discloses wherein the plate controller [PL-DEC] is configured to control the generation of the extra plate signal for reducing crosstalk between the selected plate and one or more unselected plate of the multiple plates when the plate signal changes during a portion of the memory cell access operation [since PL-DEC generates signals to select or unselect a plate and extra plate, it inherently reduces cross talk between the selected plate].
Regarding claim 6, Fig. 2 of Kuroda discloses wherein the plate controller is configured to control the generation of the plate signal and the extra plate signal such that the plate signal and the extra plate signal are complementary signals during the portion of the memory cell access operation [since P11 & P21 are not active high at the same time. When P11 is high, P21 is off. Therefore, they are complementary signals].
Regarding claim 7, Fig. 23 of Kuroda discloses sense amplifier groups [SA, within RWC-1] respectively coupled to the multiple plate groups, the sense amplifier groups each including sense amplifiers [SA] selectively coupled to memory cells of the respective plate group through digit lines [D1 to D8] of the respective plate group.
Regarding claim 8 and 15, Fig. 12 of Kuroda discloses wherein the memory cell access operation is a sensing operation including a sensing phase [READ CYCLE] and a precharge phase [PRECHARGE], and the plate controller is configured to control the generation of the plate signal and the generation of the extra plate signal [PL1, PL2] such that the plate signal falls, and the extra plate signal rises, at a beginning of the precharge phase [clearly shows in Fig. 12].
Regarding claims 9 and 16, Fig. 12 of Kuroda discloses wherein the memory cell access operation is a sensing operation including a sensing phase [READ CYCLE] and a precharge phase [PRECHARGE], and the plate controller is configured to control the generation of the plate signal and the generation of the extra plate signal such that the plate signal rises, and the extra plate signal falls, at a beginning of the precharge phase [as shows in Fig. 12, precharge operation are corresponding to plate lines PL1 and PL2].
Regarding claims 12 and 20, Fig. 2 of Kuroda discloses wherein performing the memory cell access operation comprises: selecting a plate from the multiple plates [selected by PL-DEC]; and accessing a memory cell in the plate group including the selected plate, and applying the extra plate signal [PL1 to PL3] to the extra plate comprises reducing crosstalk between the selected plate and on or more unselected plates of the multiple plates by controlling the application of the extra plate signal to the extra plate positioned near the selected plate, the crosstalk caused by the application of the plate signal to the selected plate [since PL-DEC generates signals to select or unselect a plate and extra plate, it inherently reduces cross talk between the selected plate].
Regarding claim 13, Fig. 13 of Kuroda discloses controlling the application of the plate signal and the application of the extra plate signal such that the plate signal and the extra plate signal change simultaneously during a portion of the memory cell access operation [during PRECHARGE cycle, P11 and P22 change simultaneously to maintain signal at 0].
Regarding claim 14, Fig. 13 of Kuroda discloses wherein controlling the application of the plate signal and the application of the extra plate signal comprise controlling the application of the plate signal and the application of the extra plate signal such that the plate signal and the extra plate signal are complementary signals during the portion of the memory cell access operation [during WRITE CYCLE, P11 stay at 0, but P21 at vo/2].
Regarding claim 17, Fig. 13 of Kuroda discloses generating the plate signal [P11] and the extra plate signal [P21] to be applied to the selected plate and the extra plated positioned near the selected plate, respectively, such that the plate signal rises, and the extra plate signal falls, at a beginning of the precharge phase [at beginning of PRECHARGE, P21 falls to 0].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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