DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuno et al., JP 2022141261 A (see attached English machine translation) in view of Yokoi et al., US 20180226359 A1 and Wu, et al., US 7883991 B1 (from the IDS).
Okuno teaches:
1. A method of manufacturing a semiconductor package, the method using a carrier substrate, the method comprising (see figs. 1-2):
forming a first glue layer (2) on a device substrate (1);
forming a second glue layer (3a) on the first glue layer;
coupling the device substrate (1) to a carrier substrate (4) by bonding the second glue layer to the carrier substrate;
thinning the device substrate by grinding the device substrate (e.g. see thinning in fig. 2G, page 48);
separating the carrier substrate (4) from the device substrate (1)…
Regarding claim 1:
Okuno teaches a single, integral step to remove the first glue layer (2) and the second glue layer (3) in fig. 2H.
Okuno does not expressly teach the separation occurs “at an interface between the first glue layer and the second glue layer.”
However, one of ordinary skill in the art, who is also a person of ordinary creativity, separating Okuno’s single, integral step into two separate steps would arrive at the claimed invention. For example, a first step to remove the second glue layer (3) from the first glue layer (2) at the interface and then a second step to remove the first glue layer from the device substrate (1).
It would have been obvious to one having ordinary skill in the to perform removal of Okuno’s first glue layer (2) and the second glue layer (3) as two separate steps, since constructing a formerly integral structure in various elements (e.g. one integral step into two separate steps) involves only routine skill in the art. See MPEP 2144.04, Legal Precedent as Source of Supporting Rationale, V. Making Portable, Integral, Separable, Adjustable or Continuous.
Furthermore, in an analogous art, Yokoi teaches, see fig. 3(a), separation occurs “at an interface between the first glue layer (3b) and the second glue layer (3a).” See Yokoi at para. [0035].
It would have been obvious to one having ordinary skill in the to modify Okuno with Yokoi to perform separation “at an interface between the first glue layer and the second glue layer” because preserving the first glue layer protects the device wafer during subsequent processing such as laser or plasma processing to singulate the device wafer. See Yokoi at para. [0035] – [0037], figs. 4-5.
Further regarding claim 1:
Okuno does not expressly teach:
stacking first semiconductor chips on the device substrate after the thinning the device substrate.
In an analogous art, Wu teaches:
(see fig. 2E) stacking first semiconductor chips (400) on the device substrate (200’’) after the thinning the device substrate, col 4, ln 5–22.
Okuno further teaches:
2. The method of claim 1, further comprising:
after the forming the first glue layer, curing the first glue layer at a first temperature (e.g. See Section “First adhesive layer forming step” at page 40); and
after the coupling of the device substrate to the carrier substrate, curing (See curing at page 44; Also see 14 in fig. 2F at page 48) the second glue layer at a second temperature.
Okuno further teaches:
3. The method of claim 2, wherein the first glue layer and the second glue layer comprise a same material (e.g. comprise thermoset adhesive at pages 41-42) and the first temperature and the second temperature are different from each other (e.g. See temperatures at page 40, 44 and temperatures disclose in Examples 1-4 at pages 52-55.)
Regarding claim 4:
Okuno teaches temperatures at page 40, 44 and temperatures in Examples 1-4 at pages 52-55 that overlaps the claimed range of “wherein the first temperature is 160° C. to 180° C., and the second temperature is 190° C. to 220° C”
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). “[A] prior art reference that discloses a range encompassing a somewhat narrower claimed range is sufficient to establish a prima facie case of obviousness." In re Peterson, 315 F.3d 1325, 1330, 65 USPQ2d 1379, 1382-83 (Fed. Cir. 2003). See MPEP § 2144.05, Obviousness of Ranges
Referring to MPEP § 2144.05, “…the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results over the prior art range.” (See also MPEP § 716.02 for a discussion of criticality and unexpected results.)
Yokoi further teaches:
5. The method of claim 2, further comprising, after the curing the first glue layer at the first temperature, performing a plasma treatment on a surface of the first glue layer, fig. 4(a), para. [0106].
Okuno further teaches:
6. The method of claim 1, wherein there is no release layer between the device substrate (1) and the carrier substrate (4), figs. 1-2.
Wu further teaches:
7. The method of claim 1, wherein
the device substrate (200’’) comprises a plurality of second semiconductor chips, and
the stacking the first semiconductor chips (400) includes forming a stack of the first semiconductor chips on each of the plurality of second semiconductor chips. See Wu at figs. 2E and 2K, col 4, ln 5–22, col 5, ln 15–22,
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Yokoi because “…by laminating it on a patterned surface of the semiconductor wafer, the patterned surface can be protected effectively due to a good adhesion to the patterned surface in the thinning step of the wafer. The mask-integrated surface protective tape of the present invention has a good peeling property between a mask material layer and a temporary-adhesive layer after the above-described thinning step, whereby the mask material layer can be easily exposed on top of the wafer, which allows dicing of the wafer into chips with more certainty and high precision…As a result, by processing the semiconductor wafer using the mask-integrated surface protective tape of the present invention, the occurrence of defective chips can be highly prevented.” See Yokoi at para. [0031].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Wu because “Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the limitations of the number and length of interconnections between devices as the number of devices increases. Dies-to-wafer stack bonding is one method for forming 3D ICs, wherein one or more die is bonded to a wafer, and the size of dies may be smaller than the size of chips on the wafer.” See Wu at col 1, ln 10–35.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuno in view of Yokoi and Wu, as applied to claim 1 above, in further view of Segawa et al., US 20100144120 A1.
Regarding claim 8:
Okuno, Yokoi and Wu teach all the limitations of claim 1 above, and Okuno further teaches
8. The method of claim 7, wherein
the stacking the first semiconductor chips includes applying heat and compression to the first semiconductor chips on the device substrate (e.g. See Okuno’s disclosure of temperature and pressure during bonding in Examples 1-4 at pages 52-55.)
Okuno is silent:
the applying heat and compression increases an adhesion force between the first glue layer and the second glue layer by an amount greater than 0% and less than or equal to 20% compared to the adhesion force between the first glue layer and the second glue layer before the applying the heat and compression.
In an analogous art, Segawa teaches:
“An adhesive in a film shape is applied by a thermal compression bonding to a wafer. Depending on heating, pressurization, and a period that has elapsed from a lamination, an adhesive force of an interfacial surface of a pressure sensitive adhesive layer of a dicing sheet and an adhesive layer in a film shape has a tendency to be increased.” See Segawa at para. [0004].
It would have been obvious to one of ordinary skill in the art to perform in Okuno “the applying heat and compression increases an adhesion force between the first glue layer and the second glue layer by an amount greater than 0% and less than or equal to 20% compared to the adhesion force between the first glue layer and the second glue layer before the applying the heat and compression” because Segawa teaches heating and pressurization increases the adhesive force of an adhesive layer (-i.e. glue layer).
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Segawa because understanding the increase in adhesive force caused by heating and pressurization helps to safely pick up a chip without damage. See Segawa at para. [0001], [0004], [0009].
Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuno in view of Yokoi and Wu, as applied to claim 1 above, in further view of Sakurada, US 20110217826 A1
Regarding claim 9:
Okuno, Yokoi and Wu teach all the limitations of claim 1 above, but do not expressly teach:
9. The method of claim 7, further comprising, after the stacking the first semiconductor chips on the device substrate, sealing the first semiconductor chips on the device substrate with a sealing material.
In an analogous art, Sakurada teaches:
further comprising, (see figs. 6C and 7B-7C) after the stacking the first semiconductor chips (13, 56), sealing the first semiconductor chips on the device substrate with a sealing material (64), para. [0066] – [0068].
Wu further teaches:
10. The method of claim 9, further comprising,
after the separating of the carrier substrate, (see fig. 2K) forming semiconductor packages (408) from the device substrate (200’’) and the first semiconductor chips (400),
(see fig. 2K) wherein each of the semiconductor packages (408) comprises a corresponding one of the plurality of second semiconductor chips (400) and a corresponding stack of the first semiconductor chips (e.g. from 200’’) on the corresponding one of the plurality of second semiconductor chips, figs. 2E-2K
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Sakurada to perform “after the stacking the first semiconductor chips on the device substrate, sealing the first semiconductor chips on the device substrate with a sealing material” in order to protect the semiconductor chips.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuno in view of Yokoi, Wu and Sakurada, as applied to claim 1 above, in further view of Lee, US 20170060801 A1.
Regarding claim 11:
Okuno, Yokoi, Wu and Sakurada teaches all the limitations of claim 1 and Wu further teaches the chips may be memory or logic chips at col 4, ln 5–22.
Okuno, Yokoi, Wu and Sakurada do not expressly teach:
11. The method of claim 10, wherein
each of the semiconductor packages comprises a high bandwidth memory (HBM) package,
each of the first semiconductor chips comprises a memory chip, and
each of the plurality of second semiconductor chips comprise a buffer chip.
In an analogous art, Lee teaches (see fig. 1) a high bandwidth memory (HBM) package
comprising first semiconductor chips (310-340) comprising a memory chip, and second semiconductor chips comprising a buffer chip (200). See Lee at para. [0021] – [0025],
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Lee to form “each of the semiconductor packages comprises a high bandwidth memory (HBM) package, each of the first semiconductor chips comprises a memory chip, and each of the plurality of second semiconductor chips comprise a buffer chip” because “…memory chips 310 to 340 may perform operations corresponding to the plurality of control signals CTRL transferred through the buffer chip 200 from the controller 100, and may perform an operation of storing the data DATA therein and an operation of outputting the stored data therefrom…The buffer chip 200 may be configured to transfer the data output from the…memory chips 310 to 340 to the controller 100 or transfer the data output from one of the…memory chips 310 to 340 to other memory chips.” See Lee at para. [0024] – [0025],
Claim(s) 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuno in view of Yokoi, Wu and Sakurada.
Regarding claim 12:
Okuno, Yokoi, Wu and Sakurada teach the limitations as applied to claims 1-4 and 9 above.
Regarding claim 13:
Okuno, Yokoi, Wu and Sakurada teach the limitations as applied to claim 7 above.
Regarding claim 14:
Wu further teaches:
14. The method of claim 13, further comprising: after the separating the carrier substrate, (see fig. 2K) forming semiconductor packages (408) from the device substrate (200’’) and the plurality of first semiconductor chips (400), figs. 2E-2K
Sakurada also teaches:
14. The method of claim 13, further comprising: after the separating the carrier substrate (20), forming semiconductor packages (e.g. mounting to wiring board 70) from the device substrate (e.g. bottommost 13) and the plurality of first semiconductor chips (56), figs. 4B-4C and fig. 9C.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Yokoi because “…by laminating it on a patterned surface of the semiconductor wafer, the patterned surface can be protected effectively due to a good adhesion to the patterned surface in the thinning step of the wafer. The mask-integrated surface protective tape of the present invention has a good peeling property between a mask material layer and a temporary-adhesive layer after the above-described thinning step, whereby the mask material layer can be easily exposed on top of the wafer, which allows dicing of the wafer into chips with more certainty and high precision…As a result, by processing the semiconductor wafer using the mask-integrated surface protective tape of the present invention, the occurrence of defective chips can be highly prevented.” See Yokoi at para. [0031].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Wu because “Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the limitations of the number and length of interconnections between devices as the number of devices increases. Dies-to-wafer stack bonding is one method for forming 3D ICs, wherein one or more die is bonded to a wafer, and the size of dies may be smaller than the size of chips on the wafer.” See Wu at col 1, ln 10–35.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Sakurada to perform “after the stacking the first semiconductor chips on the device substrate, sealing the first semiconductor chips on the device substrate with a sealing material” in order to protect the semiconductor chips; and “In this manner, wiring board 70 is diced into individual product forming parts 71. Product forming parts 71 each mounted with chip stack 56 are then picked up from dicing tape 86, so that it is possible to fabricate a plurality of COC semiconductor devices.” See Sakurada at para. [0086].
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuno in view of Yokoi, Wu and Sakurada, as applied to claim 12 above, in view of in further view of Lee, US 20170060801 A1.
Regarding claim 15:
Okuno, Yokoi, Wu and Sakurada teach all the limitations of claim 12 above, and
Okuno further teaches:
an external connection terminal (1a) under a lower surface of the corresponding one of the plurality of second semiconductor chips (1), fig. 2H.
Wu also teaches:
an external connection terminal (e.g. conductive balls) under a lower surface of the corresponding one of the plurality of second semiconductor chips (200’’) fig. 2A, 2E.
Sakurada further teaches:
“the sealing material to seal the stack of the plurality of first semiconductor chips”, as applied to claim 9 above.
Okuno, Yokoi, Wu and Sakurada do not expressly teach:
15. The method of claim 14, wherein
each of the semiconductor packages comprises a high bandwidth memory (HBM) package, and
the HBM package comprises a corresponding stack of the plurality of first semiconductor chips on a corresponding one of the plurality of second semiconductor chips,
In an analogous art, Lee teaches (see fig. 1) a high bandwidth memory (HBM) package
comprising a stack of first semiconductor chips (310-340) comprising a memory chip on a corresponding second semiconductor chip comprising a buffer chip (200). See Lee at para. [0021] – [0025],
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Lee to form “each of the semiconductor packages comprises a high bandwidth memory (HBM) package, and the HBM package comprises a corresponding stack of the plurality of first semiconductor chips on a corresponding one of the plurality of second semiconductor chips,” because “…memory chips 310 to 340 may perform operations corresponding to the plurality of control signals CTRL transferred through the buffer chip 200 from the controller 100, and may perform an operation of storing the data DATA therein and an operation of outputting the stored data therefrom…The buffer chip 200 may be configured to transfer the data output from the…memory chips 310 to 340 to the controller 100 or transfer the data output from one of the…memory chips 310 to 340 to other memory chips.” See Lee at para. [0024] – [0025].
Claim(s) 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuno in view of Yokoi and Wu.
Regarding claim 16:
Okuno, Yokoi and Wu teach the limitations as applied to claims 1-3 above.
Regarding claim 17:
Okuno, Yokoi and Wu teach the limitations as applied to claims 3-4 above.
Regarding claim 18:
Okuno further teaches:
18. The method of claim 17, further comprising: arranging external connection terminals (1a) on the device substrate (1) before the forming the first glue layer (2) and the second glue layer (3a) on the device substrate, wherein in the forming the first glue layer, the first glue layer (2) is formed to cover the external connection terminals (1a), figs. 2B-2C.
Regarding claim 19:
Okuno, Yokoi and Wu teach the limitations as applied to claim 6 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Yokoi because “…by laminating it on a patterned surface of the semiconductor wafer, the patterned surface can be protected effectively due to a good adhesion to the patterned surface in the thinning step of the wafer. The mask-integrated surface protective tape of the present invention has a good peeling property between a mask material layer and a temporary-adhesive layer after the above-described thinning step, whereby the mask material layer can be easily exposed on top of the wafer, which allows dicing of the wafer into chips with more certainty and high precision…As a result, by processing the semiconductor wafer using the mask-integrated surface protective tape of the present invention, the occurrence of defective chips can be highly prevented.” See Yokoi at para. [0031].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Wu because “Three-dimensional (3D) integrated circuits (ICs) are therefore created to resolve the limitations of the number and length of interconnections between devices as the number of devices increases. Dies-to-wafer stack bonding is one method for forming 3D ICs, wherein one or more die is bonded to a wafer, and the size of dies may be smaller than the size of chips on the wafer.” See Wu at col 1, ln 10–35.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuno in view of Yokoi and Wu, as applied to claim 16 above, in further view of Sakurada.
Regarding claim 20:
Okuno, Yokoi, Wu and Sakurada teach the limitations as applied to claims 7, 9 and 10 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Okuno with the teachings of Sakurada because (i) a sealing material can protect the semiconductor chips; and (ii) “In this manner, wiring board 70 is diced into individual product forming parts 71. Product forming parts 71 each mounted with chip stack 56 are then picked up from dicing tape 86, so that it is possible to fabricate a plurality of COC semiconductor devices.” See Sakurada at para. [0086].
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
1 October 2026
