DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are present for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claims 1 & 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hung et al (US 11,132,176).
Claim 1, Hung et al (Fig. 1) shows a memory cell array having a plurality of non-volatile cells (NOR-FLASH), and Fig. 4 shows each cell capable of storing 4 different storage chares *i.e., 2.5V, 3.5V, 4.5V, and 5.5V), or at least three different charge levels as claimed. Fig. 5 also shows a decoding/logic circuit for sensing & decoding each stored/voltage levels, combine the individual bits from at least three bit lines bits (B0, B1 & B2), and/or output them as a multiple digit representation (from a 3-bit register 150) as shown. Additionally, Fig. 6 also shows another combinatory logic circuit using a control logic and the three flip-flops (230-232) for combining three different bits (Bit0, Bit1, Bit2) into a three-digit string for representing a multiple-digit results as desired by the user. See below illustrations:
[AltContent: textbox (The different threshold/voltage levels
then are sensed and decoded into individual bits)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Each cell capable for storing
4 different threshold voltage levels
2.5V, 3.5V, 4.5V, and 5.5V)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: arrow]
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[AltContent: arrow][AltContent: arrow][AltContent: arrow]
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[AltContent: textbox (A multiple-digit representation is also combined from the three sensed bits, and then output to user as a 3-bit digital string
= Bit0 + Bit1 + Bit2, as 000, 001, 010, 011, 100, 101, 110 & 111, etc.
from 3 sensed currents of 3 bit lines.)]
Claim 3, if M = 2 the Fig. 8 below shows that the combinatory logic shown in Fig. 6 is configured to: receive multiple-digit representations of stored voltage values from cash of M respective memory cells in a second memory array, wherein each of the memory cells is configured to store a charge having one of at least three different charge levels; and based on the received multiple-digit representations of the stored voltage values, provide a second multiple-bit word (or 3-bit words), wherein a number of bits in the second multiple-bit word is greater than M (3 > M = 2).
[AltContent: textbox (A multiple-digit representation is also combined from the three sensed bits, to provide first and second multiple representations (Input -> Output), and then output to user as a 3-bit digital string
= Bit0 + Bit1 + Bit2, as 000, 001, 010, 011, 100, 101, 110 & 111, etc.
from 3 sensed currents of 3 bit lines.)][AltContent: arrow][AltContent: arrow]
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Claim 4, Fig. 8 shows the first multi-bit word has 2 bits (Bit1+Bit2), while the second bit word has 3 bits(EN1+EN2+EN3), and they are different from each other.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1-20 recites the integer variables N, M, L and X. However, it is unclear what are the possible range of these integer values falling into? Particularly, what are their starting values? For example, does N > 0 or N > 1? Same thing applied for M, L and X values. What are their starting values, or their cover ranges, and/or how their values compare relative to each other? Also, it is also unclear how these claimed multiple-digit representation are derived from if the starting values of M, N. L, and X are unknown.
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VIET Q NGUYEN whose telephone number is (571)272-1788. The examiner can normally be reached M-F 7:30-3PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VIET Q NGUYEN/Primary Examiner, Art Unit 2827
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