DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Chinese Patent Application No. CN202410827823.5, filed on 6/25/2024.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/29/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The title of the invention has been suggested as, “SEMICONDUCTOR PACKAGE COMPRISING A SUBSTRATE WITH A MAGNETIC EXTENSION PART AND A SEMICONDUCTOR DIE WITH A MAGNETIC EXTENSION PART, WHEREIN THE MAGNETIC EXTENSION PARTS APPLY FORCE ON EACH OTHER TO MINIMIZE THE WARPAGE OF THE SEMICONDUCTOR CHIP”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4, 6-7, 9-12, 14, 16-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ji Embodiment 1 (US 2015/0130075 A1, Embodiment shown in Fig. 34) in view of Ji Embodiment 2 (US 2015/0130075 A1, Embodiment shown in Fig. 16).
Regarding claim 1, Ji Embodiment 1 teaches a semiconductor package (comprising semiconductor chip 220 and substrate 210, Fig. 34, [0126]) comprising:
a substrate (substrate 210, Fig. 34) comprising a substrate body (substrate 210, Fig. 34), a substrate extension part (magnetic substances 211, Fig. 34, [0125]), the substrate body (substrate 210, Fig. 34) having a first surface (top surface of substrate 211, Fig. 34) and a second surface (bottom surface of substrate 211, Fig. 34) opposite to the first surface (top surface of substrate 211, Fig. 34), the substrate extension part (magnetic substances 211, Fig. 34) being on the first surface of the substrate body (top surface of substrate 211, Fig. 34), and the substrate extension part (magnetic substances 211, Fig. 34) having a first magnetism (up or down, see Figs. 17-19);
a semiconductor chip (semiconductor chip 220, Fig. 34) on the first surface of the substrate body (top surface of substrate 211, Fig. 34), the semiconductor chip comprising a chip body (semiconductor chip 220, Fig. 34) and a chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34, [0124]), the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) being on a side surface of the chip body (right and left side surfaces of the semiconductor chip 220, Fig. 34), the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) having a second magnetism (up or down, see Figs. 17-19); and
wherein the substrate extension part (magnetic substances 211, Fig. 34) and the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) overlap in a first direction (vertical direction in Fig. 34), and the substrate extension part (magnetic substances 211, Fig. 34) and the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) are spaced apart in the first direction (vertical direction in Fig. 34).
Ji Embodiment 1, however does not teach that
the substrate comprises a substrate connection terminal, the substrate connection terminal being on the second surface of the substrate body; and
a mold layer encapsulating the semiconductor chip on the first surface of the substrate body.
Ji Embodiment 2, on the other hand, teaches a semiconductor package (Fig. 16) wherein
the substrate (substrate 10, Fig. 16, [0085]) comprises a substrate connection terminal (external terminals 19, Fig. 16, [0085]), the substrate connection terminal (external terminals 19, Fig. 16) being on the second surface of the substrate body (bottom surface of the substrate 10, Fig. 16); and
a mold layer (encapsulant 18, Fig. 16, [0085]) encapsulating the semiconductor chip (first semiconductor chip 20, Fig. 16, [0085]) on the first surface of the substrate body (top surface of the substrate 10, Fig. 16).
Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention, who aims to integrate the semiconductor package of Ji Embodiment 1 with other devices to form electronic devices and protect the semiconductor package from the environment, would be motivated to include substrate connection terminals at the second surface of the substrate body in the semiconductor package of Ji Embodiment 1, as taught by Ji Embodiment 2, to provide an interface for external electrical connections, and encapsulate the semiconductor package with a mold layer, again as taught by Ji Embodiment 2, to protect the semiconductor chip from environmental factors such as external force or moisture.
Regarding claim 2, Ji Embodiment 1 in view of Ji Embodiment 2 teaches the semiconductor package of claim 1, wherein
Ji Embodiment 1further teaches that the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) is in contact with the side surface of the chip body (right side surface of the semiconductor chip 220, Fig. 34: magnetic substances 221., 222, 223, 224 are in contact with the recessed portion of the side surface).
Regarding claim 4, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor package of claim 1, wherein
Ji Embodiment 1 further teaches that
the chip body (semiconductor chip 220, see Illustrative Fig. 1 which is an annotated version of Fig. Fig. 34) comprises a plurality of first portions (first portions Illustrative Fig. 1) and a second portion (second portions Illustrative Fig. 1) between the plurality of first portions (first portions Illustrative Fig. 1), and
the chip extension part (magnetic substances 221., 222, 223, 224; Illustrative Fig. 1) is on at least one portion of the side surface of the chip body (see one portion as labeled in Illustrative Fiig. 1) corresponding to the plurality of first portions (first portions Illustrative Fig. 1).
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Regarding claim 6, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor package of claim 1, wherein
Ji Embodiment 1 further teaches that the substrate extension part (magnetic substances 211, Fig. 34) completely overlaps the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) in the first direction (vertical direction in Fig. 34).
Regarding claim 7, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor package of claim 1, wherein
Ji Embodiment 1 further teaches that
the substrate (substrate 210, Fig. 34) further comprises a substrate connector (while Ji Embodiment 1 does not explicitly disclose a substrate connector, Ji discloses that “A plurality of first connection terminals 29 may be formed between the substrate 10 and the firs semiconductor chip 20 through or in the underfill layer 17. The first through electrodes 28 may be electrically connected to the substrate 10 via the first connection terminals 29.” (see Fig. 1 where connection terminals are analogous to connection terminals 229 of Fig. 34). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the top surface of the substrate has substrate connectors) at a portion of the first surface of the substrate body (top surface of the substrate 210, Fig. 34) facing the chip body (semiconductor chip 220, Fig. 34),
the chip body (semiconductor chip 220, Fig. 34) has a first surface (top surface of semiconductor chip 220, Fig. 34) and a second surface (bottom surface of semiconductor chip 220, Fig. 34) opposite to the first surface (top surface of semiconductor chip 220, Fig. 34), the second surface of the chip body (bottom surface of semiconductor chip 220, Fig. 34) facing the substrate body (substrate 210, Fig. 34),
the semiconductor chip (semiconductor chip 220, Fig. 34) further comprises a chip pad (bottom of through electrodes 226, Fig. 34, [0125]) at the second surface of the chip body (bottom surface of semiconductor chip 220, Fig. 34) and a chip connection terminal (connection terminals 229, Fig. 34, [0125]) coupled to the chip pad (bottom surface of semiconductor chip 220, Fig. 34), and
the chip connection terminal (connection terminals 229, Fig. 34) is coupled to the substrate connector (see above).
Regarding claim 9, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor package of claim 1, wherein
Ji Embodiment further teaches that the chip body (semiconductor chip 220, Fig. 34) is a die ([0124]: “a plurality of semiconductor chips 220 may be formed on a semiconductor wafer 200.” (Fig. 32) and “the semiconductor chips 220 may be separated by cutting along the scribe lane 228.” ([0126]). Therefore, the chip body is a die).
Regarding claim 10, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor package of claim 1, wherein
the substrate extension part (magnetic substances 211, Fig. 34) and the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) are configured to:
generate a magnetic force ([0096] and Figs. 17-19) between each other based on the semiconductor chip (semiconductor chip 220, Fig. 34) being placed on the substrate body (substrate 210, Fig. 34),
wherein the magnetic force is configured correct a warpage of the chip body ([0075]: “The magnetic substances 11, 12, 13, 21, 22, and 23 may serve to temper warpage in the shape of crying (Ⴖ) (as described above) occurring in the first semiconductor chip 20.”).
Regarding claim 11, Ji Embodiment 1 teaches a semiconductor device (multi-media chip (eMMC) 1200, Fig. 35, [0127]: “FIGS. 35 to 37 are perspective views illustrating electronic apparatuses in accordance with embodiments of the inventive concept, and FIG. 38 is a system block diagram illustrating electronic apparatuses in accordance with embodiments of the inventive concept.”) comprising:
a semiconductor package (comprising semiconductor chip 220 and substrate 210, Fig. 34, [0126]) comprising:
a substrate (substrate 210, Fig. 34) comprising a substrate body (substrate 210, Fig. 34), a substrate extension part (magnetic substances 211, Fig. 34, [0125]), the substrate body (substrate 210, Fig. 34) having a first surface (top surface of substrate 211, Fig. 34) and a second surface (bottom surface of substrate 211, Fig. 34) opposite to the first surface (top surface of substrate 211, Fig. 34), the substrate extension part (magnetic substances 211, Fig. 34) being on the first surface of the substrate body (top surface of substrate 211, Fig. 34), and the substrate extension part (magnetic substances 211, Fig. 34) having a first magnetism (up or down, see Figs. 17-19);
a semiconductor chip (semiconductor chip 220, Fig. 34) on the first surface of the substrate body (top surface of substrate 211, Fig. 34), the semiconductor chip comprising a chip body (semiconductor chip 220, Fig. 34) and a chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34, [0124]), the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) being on a side surface of the chip body (right and left side surfaces of the semiconductor chip 220, Fig. 34), the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) having a second magnetism (up or down, see Figs. 17-19); and
wherein the substrate extension part (magnetic substances 211, Fig. 34) and the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) overlap in a first direction (vertical direction in Fig. 34), and the substrate extension part (magnetic substances 211, Fig. 34) and the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) are spaced apart in the first direction (vertical direction in Fig. 34).
Ji Embodiment 1, however does not teach that
the substrate comprises a substrate connection terminal, the substrate connection terminal being on the second surface of the substrate body; and
a mold layer encapsulating the semiconductor chip on the first surface of the substrate body.
Ji Embodiment 2, on the other hand, teaches a semiconductor package (Fig. 16) wherein
the substrate (substrate 10, Fig. 16, [0085]) comprises a substrate connection terminal (external terminals 19, Fig. 16, [0085]), the substrate connection terminal (external terminals 19, Fig. 16) being on the second surface of the substrate body (bottom surface of the substrate 10, Fig. 16); and
a mold layer (encapsulant 18, Fig. 16, [0085]) encapsulating the semiconductor chip (first semiconductor chip 20, Fig. 16, [0085]) on the first surface of the substrate body (top surface of the substrate 10, Fig. 16).
Accordingly, a person of ordinary skill in the art before the effective filing date of the claimed invention, who aims to integrate the semiconductor package of Ji Embodiment 1 1 with other devices to form electronic devices and protect the semiconductor package from the environment, would be motivated to include substrate connection terminals at the second surface of the substrate body in the semiconductor package of Ji Embodiment 1, as taught by Ji Embodiment 2, to provide an interface for external electrical connections, and encapsulate the semiconductor package with a mold layer, again as taught by Ji Embodiment 2, to protect the semiconductor chip from environmental factors such as external force or moisture.
Regarding claim 12, teaches the semiconductor device of claim 11, wherein the chip extension part is in contact with the side surface of the chip body.
Regarding claim 12, Ji Embodiment 1 in view of Ji Embodiment 2 teaches the semiconductor device of claim 11, wherein
Ji Embodiment 1 further teaches that the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) is in contact with the side surface of the chip body (right side surface of the semiconductor chip 220, Fig. 34: magnetic substances 221., 222, 223, 224 are in contact with the recessed portion of the side surface).
Regarding claim 14, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor device of claim 11, wherein
Ji Embodiment 1 further teaches that
the chip body (semiconductor chip 220, see Illustrative Fig. 1 which is an annotated version of Fig. Fig. 34) comprises a plurality of first portions (first portions Illustrative Fig. 1) and a second portion (second portions Illustrative Fig. 1) between the plurality of first portions (first portions Illustrative Fig. 1), and
the chip extension part (magnetic substances 221., 222, 223, 224; Illustrative Fig. 1) is on at least one portion of the side surface of the chip body (see one portion as labeled in Illustrative Fiig. 1) corresponding to the plurality of first portions (first portions Illustrative Fig. 1).
Regarding claim 16, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor device of claim 11, wherein
Ji Embodiment 1 further teaches that the substrate extension part (magnetic substances 211, Fig. 34) completely overlaps the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) in the first direction (vertical direction in Fig. 34).
Regarding claim 17, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor device of claim 11, wherein
Ji Embodiment 1 further teaches that
the substrate (substrate 210, Fig. 34) further comprises a substrate connector (while Ji Embodiment 1 does not explicitly disclose a substrate connector, Ji discloses that “A plurality of first connection terminals 29 may be formed between the substrate 10 and the firs semiconductor chip 20 through or in the underfill layer 17. The first through electrodes 28 may be electrically connected to the substrate 10 via the first connection terminals 29.” (see Fig. 1 where connection terminals are analogous to connection terminals 229 of Fig. 34). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would understand that the top surface of the substrate has substrate connectors) at a portion of the first surface of the substrate body (top surface of the substrate 210, Fig. 34) facing the chip body (semiconductor chip 220, Fig. 34),
the chip body (semiconductor chip 220, Fig. 34) has a first surface (top surface of semiconductor chip 220, Fig. 34) and a second surface (bottom surface of semiconductor chip 220, Fig. 34) opposite to the first surface (top surface of semiconductor chip 220, Fig. 34), the second surface of the chip body (bottom surface of semiconductor chip 220, Fig. 34) facing the substrate body (substrate 210, Fig. 34),
the semiconductor chip (semiconductor chip 220, Fig. 34) further comprises a chip pad (bottom of through electrodes 226, Fig. 34, [0125]) at the second surface of the chip body (bottom surface of semiconductor chip 220, Fig. 34) and a chip connection terminal (connection terminals 229, Fig. 34, [0125]) coupled to the chip pad (bottom surface of semiconductor chip 220, Fig. 34), and
the chip connection terminal (connection terminals 229, Fig. 34) is coupled to the substrate connector (see above).
Regarding claim 19, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor device of claim 11, wherein
Ji Embodiment further teaches that the chip body (semiconductor chip 220, Fig. 34) is a die ([0124]: “a plurality of semiconductor chips 220 may be formed on a semiconductor wafer 200.” (Fig. 32) and “the semiconductor chips 220 may be separated by cutting along the scribe lane 228.” ([0126]). Therefore, the chip body is a die).
Regarding claim 20, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor device of claim 11, wherein
the substrate extension part (magnetic substances 211, Fig. 34) and the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) are configured to:
generate a magnetic force ([0096] and Figs. 17-19) between each other based on the semiconductor chip (semiconductor chip 220, Fig. 34) being placed on the substrate body (substrate 210, Fig. 34),
Claim 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Ji Embodiment 1 (US 2015/0130075 A1, Embodiment shown in Fig. 34) in view of Ji Embodiment 2 (US 2015/0130075 A1, Embodiment shown in Fig. 16) as applied to claims 1-2, 4, 6, 11-12, 14, 16 above, and further in view of Ji Embodiment 3 (US 2015/0130075 A1, Fig. 10).
Regarding claim 3, while Ji Embodiment 1 in view of Ji Embodiment 2 teaches the semiconductor package of claim 1,
Ji Embodiment 1 and Ji Embodiment 2 do not teach that the chip extension part has a top surface substantially coplanar with a first surface of the chip body, the first surface of the chip body facing away from the substrate body.
Ji Embodiment 2, however, teaches a semiconductor package (Fig. 16) comprising multiple semiconductor chips (semiconductor chips 20, 70, and 80, Fig. 16, [0085]) stacked over each other by also extending the semiconductor chip extension part to include another portion (magnetic substance 25 for semiconductor chip 20 and magnetic substance 75 for semiconductor chip 70, Fig. 16. [0087]) on the top surface of the semiconductor chips.
Therefore, a person of ordinary skill in the art before the effective filing date pf the claimed invention who aims to form a semiconductor package comprising multiple semiconductor chips would be motivated to extend the semiconductor chip extension part to the top surface of the semiconductor chip in the semiconductor package of Ji Embodiment 1 in view of Ji Embodiment 2 by including a portion on the top surface of the semiconductor chip, as taught by Ji Embodiment 2. Thus, the combination of Ji Embodiment 1 and Ji Embodiment 2 teaches that the chip extension part has a top surface at the side of a first surface of the chip body (top surface of the semiconductor chip, Fig. 16), the first surface of the chip body facing away from the substrate body.
Ji Embodiment 1 and Ji Embodiment 2, however, do not teach that the chip extension part has a top surface substantially coplanar with a first surface of the chip body.
Ji Embodiment 3, however, teaches that the chip extension parts at the edges of the semiconductor chip (first magnetic substance or member 21 and a second magnetic substance or member 22, Fig. 10, [0077]) may be buried in the semiconductor chip (first semiconductor chip 20, Fig. 10, [0077]).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that embedding the chip extension parts in the semiconductor chip in the semiconductor chip of Ji Embodiment 1 and Ji Embodiment 2, as taught by Ji Embodiment 3, would decrease the height of the chip stack. Therefore, the person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to embed the chip extension parts in the semiconductor chips. Thus, the combination of Ji Embodiment 1, Ji Embodiment 2, and Ji Embodiment 3 leads to a semiconductor package where the chip extension part has a top surface substantially coplanar with a first surface of the chip body.
Regarding claim 13, while Ji Embodiment 1 in view of Ji Embodiment 2 teaches the semiconductor device of claim 11,
Ji Embodiment 1 and Ji Embodiment 2 do not teach that the chip extension part has a top surface substantially coplanar with a first surface of the chip body, the first surface of the chip body facing away from the substrate body.
Ji Embodiment 2, however, teaches a semiconductor package (Fig. 16) comprising multiple semiconductor chips (semiconductor chips 20, 70, and 80, Fig. 16, [0085]) stacked over each other by also extending the semiconductor chip extension part to include another portion (magnetic substance 25 for semiconductor chip 20 and magnetic substance 75 for semiconductor chip 70, Fig. 16. [0087]) on the top surface of the semiconductor chips.
Therefore, a person of ordinary skill in the art before the effective filing date pf the claimed invention who aims to form a semiconductor package comprising multiple semiconductor chips would be motivated to extend the semiconductor chip extension part to the top surface of the semiconductor chip in the semiconductor package of Ji Embodiment 1 in view of Ji Embodiment 2 by including a portion on the top surface of the semiconductor chip, as taught by Ji Embodiment 2. Thus, the combination of Ji Embodiment 1 and Ji Embodiment 2 teaches that the chip extension part has a top surface at the side of a first surface of the chip body (top surface of the semiconductor chip, Fig. 16), the first surface of the chip body facing away from the substrate body.
Ji Embodiment 1 and Ji Embodiment 2, however, do not teach that the chip extension part has a top surface substantially coplanar with a first surface of the chip body.
Ji Embodiment 3, however, teaches that the chip extension parts at the edges of the semiconductor chip (first magnetic substance or member 21 and a second magnetic substance or member 22, Fig. 10, [0077]) may be buried in the semiconductor chip (first semiconductor chip 20, Fig. 10, [0077]).
A person of ordinary skill in the art before the effective filing date of the claimed invention would realize that embedding the chip extension parts in the semiconductor chip in the semiconductor chip of Ji Embodiment 1 and Ji Embodiment 2, as taught by Ji Embodiment 3, would decrease the height of the chip stack. Therefore, the person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to embed the chip extension parts in the semiconductor chips. Thus, the combination of Ji Embodiment 1, Ji Embodiment 2, and Ji Embodiment 3 leads to a semiconductor device where the chip extension part has a top surface substantially coplanar with a first surface of the chip body.
Claim 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ji Embodiment 1 (US 2015/0130075 A1, Embodiment shown in Fig. 34) in view of Ji Embodiment 2 (US 2015/0130075 A1, Embodiment shown in Fig. 16) as applied to claims 1-2, 4, 6-7, 9-12, 14, 16-17, and 19-20 above, and further in view of Kang (WO 2005122706 A2).
Regarding claim 8, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor package of claim 1,
wherein the substrate extension part (magnetic substances 211, Fig. 34) comprises a first magnetic material ([0059]: ”each of the magnetic substances 11, 12, 13, 21, 22, and 23 may include Ferrite, SmCo, AlNiCo, NdFeB, or a combination thereof.”), and
wherein the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) comprises a second magnetic material ([0059]: “each of the magnetic substances 11, 12, 13, 21, 22, and 23 may include Ferrite, SmCo, AlNiCo, NdFeB, or a combination thereof.”).
Neither Ji Embodiment 1 nor Ji Embodiment 2, however, teaches that
the chip extension part comprises a second resin.
Kang, on the other hand, teaches forming a chip extension part (first magnetic body 110a, Figs. 3-4, [44]) on a semiconductor chip (semiconductor device 102, Figs. 3-4, [44]), wherein
the chip extension part comprises a second resin ([44]: “Another method to form the film of magnetic material 110 is to use magnetic powder dispersed in a resin such as polyimide or benzocyclobutene (BCB ).”)
Kang further discloses that the method includes spin coating the resin containing magnetic powder on the wafer and curing the resin ([44]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use the method of Kang to form the chip extension part in the semiconductor package of Ji Embodiment 1 in view of Ji Embodiment 2 which simplifies and speeds up the manufacturing steps by removing the necessity of film deposition in a deposition chamber. Furthermore, selection of a known material and method based on its suitability for its intended use supports a prima facie obviousness (see MPEP 2144.06), as it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select a resin based magnetic material to form the chip extension part to obtain the predictable result of forming a magnetic force between the semiconductor chip and the substrate (see Kang’s Fig. 15). Furthermore, the Applicant did not provide any criticality for the material chosen material.
Regarding claim 18, Ji Embodiment 1 and Ji Embodiment 2 teaches the semiconductor package of claim 11,
wherein the substrate extension part (magnetic substances 211, Fig. 34) comprises a first magnetic material ([0059]: ”each of the magnetic substances 11, 12, 13, 21, 22, and 23 may include Ferrite, SmCo, AlNiCo, NdFeB, or a combination thereof.”), and
wherein the chip extension part (magnetic substances 221., 222, 223, 224; Fig. 34) comprises a second magnetic material ([0059]: “each of the magnetic substances 11, 12, 13, 21, 22, and 23 may include Ferrite, SmCo, AlNiCo, NdFeB, or a combination thereof.”).
Neither Ji Embodiment 1 nor Ji Embodiment 2, however, teaches that
the chip extension part comprises a second resin.
Kang, on the other hand, teaches forming a chip extension part (first magnetic body 110a, Figs. 3-4, [44]) on a semiconductor chip (semiconductor device 102, Figs. 3-4, [44]), wherein
the chip extension part comprises a second resin ([44]: “Another method to form the film of magnetic material 110 is to use magnetic powder dispersed in a resin such as polyimide or benzocyclobutene (BCB ).”)
Kang further discloses that the method includes spin coating the resin containing magnetic powder on the wafer and curing the resin ([44]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use the method of Kang to form the chip extension part in the semiconductor device of Ji Embodiment 1 in view of Ji Embodiment 2 which simplifies and speeds up the manufacturing steps by removing the necessity of film deposition in a deposition chamber. Furthermore, selection of a known material and method based on its suitability for its intended use supports a prima facie obviousness (see MPEP 2144.06), as it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select a resin based magnetic material to form the chip extension part to obtain the predictable result of forming a magnetic force between the semiconductor chip and the substrate (see Kang’s Fig. 15). Furthermore, the Applicant did not provide any criticality for the chosen material.
Allowable Subject Matter
Claims 5 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, claim 5, disclosing that “the chip extension part covers the entire side surface of the chip body” would be allowable if this limitation is incorporated in a claim combining claims 1 and 5.
As closest prior art, Ji Embodiment 1 in view of Ji Embodiment 2 teaches all the limitations of claim 1 (see claim 1 rejection above), however fails to teach that the chip extension part covers the entire side surface of the chip body.
There has been no prior art identified that can modify Ji Embodiment 1 and Ji Embodiment 2 further to meet the limitation above. Therefore, claim 5 is objected.
Regarding claim 15, claim 15, disclosing that “the chip extension part covers the entire side surface of the chip body” would be allowable if this limitation is incorporated in a claim combining claims 1 and 5.
As closest prior art, Ji Embodiment 1 in view of Ji Embodiment 2 teaches all the limitations of claim 11 (see claim 11 rejection above), however fails to teach that the chip extension part covers the entire side surface of the chip body.
There has been no prior art identified that can modify Ji Embodiment 1 and Ji Embodiment 2 further to meet the limitation above. Therefore, claim 15 is objected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Chun (US 2015/0115468 A1) teaches a semiconductor package comprising magnetic extension portions for correcting warpage, which is relevant for all claims.
Bae (KR 2012004884 A) teaches a semiconductor package comprising magnetic extension portions for correcting warpage, which is relevant for all claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
