DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nishida et al. (2020/0194446, hereafter Nishida).
Regarding claim 1, Nishida discloses a memory device, comprising: an alternating stack of insulating layers and electrically conductive layers (55, par. 0140); a memory opening vertically extending through the alternating stack (par. 0140); and a memory opening fill structure located in the memory opening and comprising, from outside to inside, a memory film (50), and a vertical semiconductor channel (60) (Fig. 7D).
Nishida fails to explicitly disclose a core-side charge trapping material layer that vertically extends through at least a first subset of the electrically conductive layers, and a dielectric core.
However, Nishida provides a different embodiment that teaches a core-side charge trapping material layer (261) that vertically extends through at least a first subset of the electrically conductive layers, and a dielectric core (262, par. 0141) (Fig. 7D).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida by providing a core-side charge trapping material layer in order to create a split storage architecture that doubles charge storage capacity and enhances retention.
Regarding claim 13, Nishida discloses a memory device wherein: the dielectric core comprises silicon oxide (262, Fig. 7C-7D, par. 0135); and the core-side charge trapping material layer comprises silicon nitride, aluminum oxide, or silicon oxynitride (261, Fig. 7C-7D, par. 0138).
Regarding claim 15, Nishida discloses a memory device further comprising the memory film comprises a layer stack that comprises a tunneling dielectric layer (56, Fig. 5H) in contact with an outer sidewall of the vertical semiconductor channel (602/601, Fig. 5H), a charge storage layer (54, Fig. 5H) in contact with an outer sidewall of the tunneling dielectric layer, and a blocking dielectric layer (52, Fig. 5H) in contact with an outer sidewall of the charge storage layer (par. 0103).
Nishida fails to explicitly disclose a dielectric liner located between the core-side charge trapping material layer and the vertical semiconductor channel.
However, Nishida provides a different embodiment that teaches a dielectric liner (161, Fig. 5H, par. 0117) located between (from 56 between 60 and 54, Fig. 5H) the core-side charge trapping material layer (261, Fig. 7D) and the vertical semiconductor channel (602/601, Fig. 5H).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida by providing a liner between the trapping layer and semiconductor channel in order to act as a barrier that regulates carrier injection during write/erase operations and prevents leakage.
Claims 2-8 are rejected under 35 U.S.C. 103 as being unpatentable over Nishida in view of Pang et al. (2016/0307915, hereafter Pang).
Regarding claim 2, Nishida, discussed above, fails to disclose a memory device wherein the core-side charge trapping material layer does not vertically extend through a second subset of the electrically conductive layers.
However, Pang teaches a memory device wherein the core-side charge trapping material layer does not vertically extend through a second subset of the electrically conductive layers (par. 0049).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Pang by having the charge trapping layer extend through a subset of conductive layers in order to isolate individual storage nodes and prevent vertical charge migration along the channel length.
Regarding claim 3, Nishida fails to disclose a memory device wherein the second subset of the electrically conductive layers comprises a topmost electrically conductive layer of the electrically conductive layers.
However, Pang teaches a memory device wherein the second subset of the electrically conductive layers comprises a topmost electrically conductive layer (SGD1, Fig. 6D) of the electrically conductive layers.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Pang by having the subset include a topmost conductive layer in order to eliminate parasitic charge storage and unwanted threshold voltage shifts, preventing uncontrolled leakage and ensuring proper cut-off.
Regarding claim 4, Nishida fails to disclose a memory device wherein the second subset of the electrically conductive layers comprises at least two drain side select gate electrodes.
However, Pang teaches a memory device wherein the second subset of the electrically conductive layers comprises at least two drain side select gate electrodes (SGD1/SGD2, Fig. 6D).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Pang by having the subset include drain side select gate electrodes in order to ensure pure transistor performance across select module, preventing accidental electron trapping.
Regarding claim 5, Nishida fails to disclose a memory device wherein the second subset of the electrically conductive layers further comprises at least one dummy word line, and the first subset of the electrically conductive layers comprises word lines.
However, Pang teaches a memory device wherein the second subset of the electrically conductive layers further comprises at least one dummy word line (DWLL1a, Fig. 6D), and the first subset of the electrically conductive layers comprises word lines (WLL0-WLL10, Fig. 6D).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Pang by including a dummy word line in the second subset while the first subset includes word lines in order to prevent parasitic charge accumulation near the memory array boundary, while having word lines is required for data retention.
Regarding claim 6, Nishida fails to disclose a memory device wherein the second subset of the electrically conductive layers comprises a bottommost electrically conductive layer of the electrically conductive layers.
However, Pang teaches a memory device wherein the second subset of the electrically conductive layers comprises a bottommost electrically conductive layer (SGS1, Fig. 6D, par. 0185-0186) of the electrically conductive layers.
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Pang by including a bottommost conductive layer in the second subset in order to prevent unwanted threshold voltage shifts in the source select transistors, ensuring consistent source line cut-off, low leakage and reliable read/erase operations.
Regarding claim 7, Nishida fails to disclose a memory device wherein the second subset of the electrically conductive layers comprises at least two source side select gate electrodes.
However, Pang teaches a memory device wherein the second subset of the electrically conductive layers comprises at least two source side select gate electrodes (SGS1/SGS2, Fig. 6D).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Pang by including in the second subset two source side gate electrodes in order to prevent unwanted threshold voltage shifts in the source select transistors, ensuring consistent source line cut-off, low leakage and reliable read/erase operations.
Regarding claim 8, Nishida fails to disclose a memory device wherein the second subset of the electrically conductive layers comprises all source side select gate electrodes and all drain side select gate electrodes, and the first subset of the electrically conductive layers comprises active word lines.
However, Pang teaches a memory device wherein the second subset of the electrically conductive layers comprises all source side select gate electrodes and all drain side select gate electrodes (par. 0049), and the first subset of the electrically conductive layers comprises active word lines (WLL0-WLL10, Fig. 4E, 6D; par. 0132).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Pang by including all source and drain side electrodes in the subset while the remaining layers include word lines in order to ensure that all select transistors function strictly as switching gates rather than memory cells, preserving predictability and preventing parasitic charge trapping.
Claims 9-12 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Nishida in view of Sakotsubo (2022/0189981, hereafter Sakotsubo).
Regarding claim 9, Nishida, discussed above, fails to explicitly disclose a memory device wherein the dielectric core comprises: a primary dielectric core portion that is laterally surrounded by the core-side charge trapping material layer.
However, Nishida provides a different embodiment that teaches a memory device wherein the dielectric core comprises: a primary dielectric core portion (262, Fig. 7D, par. 0141) that is laterally surrounded by the core-side charge trapping material layer (261, Fig. 7D, par. 0138).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida by providing a core-side charge trapping material layer in order to create a split storage architecture that doubles charge storage capacity and enhances retention.
Nishida also fails to disclose a complementary dielectric core portion that overlies or underlies the primary dielectric core portion.
However, Sakotsubo teaches a complementary dielectric core portion (72) that overlies or underlies the primary dielectric core portion (62) (Fig. 14A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Sakotsubo by providing a complementary core above/below the primary core in order to maintain uniform material properties and structural continuity, preventing mechanical stress and interface defects.
Regarding claim 10, Nishida discloses a memory device wherein: the memory opening fill structure (49) comprises a drain region (63) contacting a first end portion of the vertical semiconductor channel (602) (Fig. 7D).
Nishida fails to disclose the complementary dielectric core portion contacts the drain region.
However, Sakotsubo teaches the complementary dielectric core portion (72) contacts the drain region (63) (Fig. 14A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Sakotsubo by providing the complementary core in contact with the drain region in order to serve as a continuous structural pillar while facilitating a stable interface.
Regarding claim 11, Nishida fails to disclose a memory device further comprising: additional memory openings vertically extending through the alternating stack; additional memory opening fill structures located in the additional memory openings and comprising a respective additional memory film and a respective additional vertical semiconductor channel; and a source layer contacting second end portions of the vertical semiconductor channel and the additional vertical semiconductor channels.
However, Sakotsubo teaches a memory device further comprising: additional memory openings vertically extending through the alternating stack (Fig. 39); additional memory opening fill structures located in the additional memory openings and comprising a respective additional memory film (50) and a respective additional vertical semiconductor channel (60); and a source layer (108) contacting second end portions of the vertical semiconductor channel and the additional vertical semiconductor channels (Fig. 39).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Sakotsubo by providing additional openings with the memory fill structure in order to increase mechanical stability and uniform etch and deposition loading across the stack.
Regarding claim 12, Nishida fails to disclose a memory device wherein the complementary dielectric core portion contacts the source layer.
However, Sakotsubo teaches a memory device wherein the complementary dielectric core portion (22) contacts the source layer (108) (Fig. 39).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Sakotsubo by providing a complementary core contacting the source layer in order to maintain uniform material properties and structural continuity, preventing mechanical stress and interface defects, and provide a stable structural anchor while facilitating a defect-free interface.
Regarding claim 17, Nishida discloses method of forming a memory device, comprising: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as or are subsequently replaced with electrically conductive layers (par. 0082, 0084, 0086); forming a memory opening through the alternating stack (par. 0096); forming a memory film (par. 0114), a vertical semiconductor channel (602, Fig. 7D), and a primary dielectric core portion (262, Fig. 7D).
Nishida fails to explicitly disclose a core-side charge trapping material layer.
However, Nishida provides a different embodiment that teaches a core-side charge trapping material layer (261, Fig. 7D, par. 0134).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida by providing a core-side charge trapping material layer in order to create a split storage architecture that doubles charge storage capacity and enhances retention.
Nishida also fails to disclose reducing vertical extents of the core-side charge trapping material layer and the primary dielectric core portion at least by a sum of a thickness of one of the insulating layers and a thickness of one of the spacer material layers; and forming a complementary dielectric core portion on the primary dielectric core portion within a volume that is laterally surrounded by a cylindrical segment of an inner sidewall of the vertical semiconductor channel in the memory opening.
However, Sakotsubo teaches reducing vertical extents of the core-side charge trapping material layer and the primary dielectric core portion at least by a sum of a thickness of one of the insulating layers and a thickness of one of the spacer material layers (Fig. 12A, par. 0175); and forming a complementary dielectric core portion (72) on the primary dielectric core portion (62) within a volume that is laterally surrounded by a cylindrical segment of an inner sidewall of the vertical semiconductor channel (60) in the memory opening (Fig. 13A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Sakotsubo by replacing the removed charge trapping layer with a complementary core surrounded by the semiconductor channel in order to ensure a continuous mechanical support while keeping the channel thin and uniform for optimal gate control.
Regarding claim 18, Nishida fails to disclose a method further comprising forming a drain region on the complementary dielectric core portion and on a first end portion of the vertical semiconductor channel.
However, Sakotsubo teaches a method further comprising forming a drain region (63) on the complementary dielectric core portion (72) and on a first end portion of the vertical semiconductor channel (60) (Fig. 14A, par. 0178).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Sakotsubo by providing the drain on the complementary core and end of the semiconductor channel in order to serve as a continuous structural pillar while facilitating a stable interface.
Regarding claim 19, Nishida fails to disclose a method further comprising forming a source layer on the complementary dielectric core portion and on a second end portion of the vertical semiconductor channel.
However, Sakotsubo teaches a method further comprising forming a source layer (108) on the complementary dielectric core portion (22) and on a second end portion of the vertical semiconductor channel (60) (Fig. 39, par. 0230-0231).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Sakotsubo by having the source layer on the complementary core and semiconductor channel in order to provide a stable structural anchor while facilitating a defect-free interface.
Regarding claim 20, Nishida discloses a method wherein: the primary dielectric core (262, Fig. 7D) comprises silicon oxide (par. 0133); the core-side charge trapping material layer (261, Fig. 7D) comprises silicon nitride, aluminum oxide, or silicon oxynitride (par. 0131).
Nishida fails to disclose the complementary dielectric core comprises silicon oxide; and the vertical extent of the core-side charge trapping material layer is reduced such that the core-side charge trapping material layer vertically extends through a first subset of the electrically conductive layers and does not vertically extend through a second subset of the electrically conductive layers.
However, Sakotsubo teaches the complementary dielectric core comprises silicon oxide (par. 0175); and the vertical extent of the core-side charge trapping material layer is reduced such that the core-side charge trapping material layer (taught above, represented by 54) vertically extends through a first subset of the electrically conductive layers and does not vertically extend through a second subset of the electrically conductive layers (Fig. 11A).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Sakotsubo by including a silicon oxide core and having the charge trapping layer extend through a subset of conductive layers in order to implement electrically inert, low-stress dielectric that efficiently fills memory holes without parasitic capacitance or interference and isolate individual storage nodes and prevent vertical charge migration along the channel length.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Nishida in view of Song et al. (2020/0185408, hereafter Song).
Regarding claim 14, Nishida discloses a memory device wherein: the dielectric core comprises silicon oxide (262, Fig. 7D, par. 0138).
Nishida fails to disclose the core-side charge trapping material layer comprises a layer stack including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer located between the first and the second silicon nitride layers.
However, Song teaches the core-side charge trapping material layer comprises a layer stack including a first silicon nitride layer, a second silicon nitride layer, and a silicon oxynitride layer located between the first and the second silicon nitride layers (par. 0063).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Song by including a charge trapping layer with a silicon nitride, silicon oxynitride, silicon nitride stack in order to utilize varying energy band offsets and oxygen profiles to optimize trade-offs between deep electron trapping efficiency, retention performance, and high-speed write/erase functionality.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Nishida in view of Liu et al. (2017/0117289, hereafter Liu).
Regarding claim 16, Nishida, discussed above, fails to disclose a method of operating the memory device comprising erasing the memory device by applying an erase voltage to the memory device to move electrons from the memory film through the vertical semiconductor channel into the core-side charge trapping material layer.
However, Liu teaches a method of operating the memory device comprising erasing the memory device by applying an erase voltage to the memory device to move electrons from the memory film through the vertical semiconductor channel into the core-side charge trapping material layer (par. 0057).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Nishida with Liu by providing an erase voltage that moves the electrons to the charge trapping layer in order to restore the memory cell to a low-threshold erased state.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M BRECHT whose telephone number is (571)272-9634. The examiner can normally be reached Mon-Fri: 7:30am - 5pm.
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/C.M.B./ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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