DETAILED ACTION
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based on an application filed in the Republic of Korea on February 15, 2024, and receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. It should be noted that in order to effectively benefit from the foreign priority date, an English translation of the certified copy (of the foreign application as filed) filed together with a statement that the translation of the certified copy is accurate must be presented.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on July 29, 2024 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
- - Manufacturing Method Of Memory Device Including Implanting N-Type Impurities In A First Crystallized Area Of A Substrate - -
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 13, the limitation “after removing the second substrate” lacks antecedent basis as opposed to the previously established “removing at least a portion of the second substrate.” (Claim 1).
For the purpose of this Office Action, the Examiner will read the limitation “after removing the second substrate” of Claim 13 as --after removing at least a portion of the second substrate--
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 9, 11, 13-14, 18, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. Pub. 2020/0357771).
Regarding Claim 1, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), the method comprising:
-forming a peripheral circuit ((P_CHIP); Fig. 2C, Paragraph [0054]) over a first substrate ((200)/(30); Figs. 1 and 2C, Paragraphs [0034] and [0054]);
-forming a first source line ((12); Fig. 2A, Paragraph [0041]) over a second substrate (comprising (10) and (11); Fig. 2A, Paragraph [0041]);
-forming a memory cell array ((C_CHIP); Fig. 2A, Paragraph [0041]) including gate lines ((23); Fig. 2A, Paragraph [0044]), cell plugs ((160) corresponding to (26), (25), and (24), hereinafter (PL); Figs. 1 and 2A, Paragraph [0027] and [0045]) extending through the gate lines (23), and bit lines (e.g. (142) as part of (14); Figs. 1 and 2A, Paragraphs [0031] and [0048]) electrically coupled to the cell plugs (PL) that protrude (Fig. 1, Paragraph [0045]) into the first source line (12);
-bonding the memory cell array (C_CHIP) to the peripheral circuit (P_CHIP) (Paragraph [0056]); and
-removing at least a portion of the second substrate ((10) and (11); Fig. 2B, Paragraph [0052]).
Regarding Claim 6, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 1, wherein:
-removing at least a portion of the second substrate (specifically portion (11)) is performed utilizing a wet etching process (Paragraph [0052]).
Regarding Claim 9, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 1, wherein:
-forming the peripheral circuit (P_CHIP) comprises: forming transistors ((TR); Fig. 2C, Paragraph [0054]) and contacts (e.g. (242)-(244) as part of (34); Figs. 1 and 2C, Paragraphs [0034] and [0054]) over the first substrate (200)/(30); and
-forming first bonding pads ((35)/(250); Figs. 1 and 2C, Paragraphs [0034] and [0055]) on outermost contacts among the contacts (e.g. (244); Fig. 1).
Regarding Claim 11, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 1, wherein:
- the forming the memory cell array (C_CHIP) comprises:
-forming the gate lines (23) and the cell plugs (PL) over the first source line (12);
-forming the bit lines ((142) as part of (14)) coupled to the cell plugs (PL); and
-forming second bonding pads coupled to the bit lines ((15)/(150); Figs. 1 and 2C, Paragraphs [0033] and [0055]).
Regarding Claim 13, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 1, wherein:
-after removing at least a portion of the second substrate ((10) and (11)), forming a second source line ((42A); Fig. 3B, Paragraph [0062]) over (e.g. over the bottom surface and replacing the top portion) the first source line ((12) as corresponding to (42); Fig. 3A, Paragraphs [0060] and [0061]) exposed by removing the second substrate ((10) and (11) corresponding to (40) and (41); Paragraph [0061]).
Regarding Claim 14, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 13, wherein:
-the second source line includes polysilicon (Poly-Si). (Paragraph [0062]).
Regarding Claim 18, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 1, further comprising:
- flipping the memory cell array ((C_CHIP); Paragraph [0051]) including the first source line (12) such that the second substrate is located at an opposite end of the memory cell array than where the second substrate was located prior to flipping.
Regarding Claim 23, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), the method comprising:
-forming a peripheral circuit ((P_CHIP); Fig. 2C, Paragraph [0054]) over a first substrate ((200)/(30); Figs. 1 and 2C, Paragraphs [0034] and [0054]);
-implanting first impurities (into (12); Fig. 2B, Paragraph [0053]) into a second substrate (Comprising (10), (11), and (12); Fig. 2A, Paragraph [0041]) to form a first source line (e.g. (12A); Fig. 2B, Paragraph [0053]);
-forming a memory cell array ((C_CHIP); Fig. 2A, Paragraph [0041]) over the second substrate ((10), (11), and (12)) such that cell plugs ((160) corresponding to (26), (25), and (24), hereinafter (PL); Figs. 1 and 2A, Paragraph [0027] and [0045]) extend (Fig. 1, Paragraph [0045]) into the first source line (12A); (Examiner notes the claim includes no chronological limitations, i.e. the memory cell array need not be formed after the first source line)
-bonding the memory cell array (C_CHIP) to the peripheral circuit (P_CHIP) (Paragraph [0056]); and
-removing at least a portion of the second substrate ((10) and (11); Fig. 2B, Paragraph [0052]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 5, 7, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Oh et al. (U.S. Pub. 2023/0137896), hereinafter Oh.
Regarding Claim 2, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 1, wherein:
-the source layer is made of a polysilicon layer (Paragraph [0043]) – Examiner notes the undoped polysilicon layer, prior to it being made a source layer, may be a sublayer of the second substrate)
-the source layer includes N-type impurities (Paragraph [0026])
but fails explicitly teach:
forming the first source line comprises: implanting first impurities into the second substrate; and crystallizing an area where the first impurities are implanted.
Oh teaches a method of manufacturing a source layer ((185); Figs. 8A-8C, Paragraph [0084]) as part of a memory device (Fig. 4, Paragraph [0045]):
forming the first source line (185) comprises: implanting first impurities (N-type, Paragraph [0035]) into the second substrate ((185AL) ‘semiconductor material made of silicon’; Paragraph [0035]); and crystallizing an area where the first impurities are implanted ((185A1); Fig. 8B, Paragraph [0089]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Oh into the method of Kim such that forming the first source line comprises: implanting first impurities into the second substrate; and crystallizing an area where the first impurities are implanted. This would be due to the fact that doing so would improve uniformity of the diffusion depth (Oh, Paragraph [0094]).
Regarding Claim 3, Kim as modified by Oh teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 2, wherein:
-the first impurities include N-type impurities (Oh, Paragraph [0035]).
Regarding Claim 5, Kim as modified by Oh teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 2, wherein:
-a heat treatment process is performed to crystallize the area where the first impurities are implanted (Oh, Paragraphs [0056] and [0089] – compare to instantaneous Specification Paragraph [0065]).
Regarding Claim 7, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 1, but does not explicitly teach:
-removing at least a portion of the second substrate is performed by a chemical mechanical polishing (CMP) process.
Oh teaches a method of manufacturing a memory device (Fig. 4, Paragraph [0045]) wherein:
-removing at least a portion of the second substrate ((101); Fig. 7C-7D, Paragraph [0083]) is performed by a chemical mechanical polishing (CMP) process (Paragraph [0058]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Oh into the method of Kim such that removing at least a portion of the second substrate is performed by a chemical mechanical polishing (CMP) process. This would be due to the fact that doing so would produce the predictable result of incorporating a viable method for removing at least a portion of the second substrate.
Regarding Claim 8, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 1, wherein:
- a grinding process and a wet etching process are sequentially performed to remove at least a portion of the second substrate (Paragraph [0052]).
But does not explicitly teach:
-a chemical mechanical polishing (CMP) process
Oh teaches a method of manufacturing a memory device (Fig. 4, Paragraph [0045]) wherein:
-removing at least a portion of the second substrate ((101); Fig. 7C-7D, Paragraph [0083]) is performed by a chemical mechanical polishing (CMP) process (Paragraph [0058]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Oh into the method of Kim such that removing at least a portion of the second substrate is performed by a chemical mechanical polishing (CMP) process, thus resulting in the limitation of a chemical mechanical polishing (CMP) process and a wet etching process are sequentially performed to remove at least a portion of the second substrate. This would be due to the fact that doing so would produce the predictable result of incorporating a viable method for removing at least a portion of the second substrate.
Claims 19-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Oh et al. (U.S. Pub. 2023/0137896), hereinafter Oh.
Regarding Claim 19, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), the method comprising:
-forming a peripheral circuit ((P_CHIP); Fig. 2C, Paragraph [0054]) over a first substrate ((200)/(30); Figs. 1 and 2C, Paragraphs [0034] and [0054]);
-forming a first source line ((12); Fig. 2A, Paragraph [0041]) over a second substrate (comprising (10) and (11); Fig. 2A, Paragraph [0041]);
-forming a memory cell array ((C_CHIP); Fig. 2A, Paragraph [0041]) over the first source line (12);
-bonding the memory cell array (C_CHIP) to the peripheral circuit (P_CHIP) (Paragraph [0056]); and
-removing a portion of the second substrate ((10) and (11); Fig. 2B, Paragraph [0052]).
Kim further teaches:
-the source layer is made of a polysilicon layer (Paragraph [0043]) – Examiner notes the undoped polysilicon layer, prior to it being made a source layer, may be a sublayer of the second substrate)
-the source layer includes N-type impurities (Paragraph [0026])
Kim does not explicitly teach:
-performing an ion implantation process on a second substrate
Oh teaches a method of manufacturing a source layer ((185); Figs. 8A-8C, Paragraph [0084]) as part of a memory device (Fig. 4, Paragraph [0045]) comprising:
implanting first impurities (N-type, Paragraph [0035]) into the second substrate ((185AL) ‘semiconductor material made of silicon’; Paragraph [0035])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Oh into the method of Kim such that it comprises performing an ion implantation process on a second substrate. Necessarily, the limitation “forming a memory cell array over the ion-implanted second substrate” would be present by the incorporation. This would be due to the fact that doing so would improve uniformity of the diffusion depth (Oh, Paragraph [0094]).
Regarding Claim 20, Kim as modified by Oh teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 19, wherein:
-the ion implantation process comprises implanting N-type impurities into a portion of the second substrate (Oh, Paragraph [0035]).
Regarding Claim 21, Kim as modified by Oh teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 19, wherein:
wherein a section (modified Kim, (12)) of the second substrate (modified Kim, comprising (10), (11), and pre/post-implantation (12)) over which the ion implantation process is performed remains after removing the portion of the second substrate (modified Kim, removal of (10) and (11)).
Regarding Claim 22, Kim as modified by Oh teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 19, further comprising:
- flipping the memory cell array (Modified Kim, (C_CHIP); Paragraph [0051]) such that the second substrate is located at an opposite end of the memory cell array than where the second substrate was located prior to flipping.
Claims 10 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Choi (U.S. Pub. 2022/0189985).
Regarding Claim 10, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 9, but does not explicitly teach:
-the first bonding pads include copper (Cu).
Choi teaches a method of manufacturing a memory device (Figs. 2A-2F, Paragraph [0064]), wherein:
-the first bonding pads ((BP1); Fig. 2C, Paragraph [0031]) include copper (Cu).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Choi into the method of Kim such that the first bonding pads include copper (Cu). This would be due to the fact that doing so would produce the predictable result of incorporating a viable conducting material in forming the first bonding pads.
Regarding Claim 12, Kim teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 11, but does not explicitly teach:
-the second bonding pads include copper (Cu).
Choi teaches a method of manufacturing a memory device (Figs. 2A-2F, Paragraph [0064]), wherein:
-the seconding bonding pads ((BP2); Fig. 2B, Paragraph [0033]) include copper (Cu).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Choi into the method of Kim such that the second bonding pads include copper (Cu). This would be due to the fact that doing so would produce the predictable result of incorporating a viable conducting material in forming the second bonding pads.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Oh as applied to claim 2 above, and further in view of Sung et al. (US 2018/0337054 A1), hereinafter referred to as ‘Sung’.
Regarding Claim 4, Kim as modified by Oh teaches a method (Figs. 2A-4B, Paragraph [0016]) of manufacturing a memory device (Fig. 1, Paragraph [0018]), of Claim 2, but neither Kim nor Oh explicitly teach:
-the first impurities include phosphorus (P) ions or arsenic (As) ions.
Sung teaches a method of manufacturing a conductive silicon source layer ((50); Fig. 5, Paragraph [0052]), wherein:
-the impurities include phosphorus (P) ions or arsenic (As) ions (Paragraph [0052]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Sung into the method of Kim as modified by Oh such that the first impurities include phosphorus (P) ions or arsenic (As) ions. This would be due to the fact that doing so would produce the expected result of utilizing applicable N-type doping for the source layer.
Allowable Subject Matter
Claims 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 15, the best prior art of record does not teach or fairly suggest, along with the other claimed features, which are necessary in informing the methodology, a method of manufacturing a memory device comprising:
-leaving a section of the second substrate such that the first source line is not exposed; and
-forming a third source line by implanting second impurities into the section of the second substrate.
Regarding Claims 16 and 17, the claims are allowable based on their dependence on Claim 15.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRI MIHALIOV whose telephone number is (571)270-5220. The examiner can normally be reached weekdays 7:30 - 17:30 US Eastern Time.
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/DMITRI MIHALIOV/ Examiner, Art Unit 2812
/SCOTT B GEYER/ Primary Examiner, Art Unit 2812
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