DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US 20240145400 A1.
Regarding claim 11:
Kim teaches (see fig. 6 annotated below)
a first structure (first GS2) formed in a cell array region (R1) of a substrate (101),…
a first dummy structure (KC2 at first GS2) formed in an alignment area (R2) of the substrate…
Kim does not expressly teach:
“a second structure arranged on the first structure, and a third structure arranged on the second structure
a second dummy structure arranged on the first dummy structure, and a third dummy structure arranged on the second dummy structure”
Referring to MPEP § 2141, Examination Guidelines for Determining Obviousness Under 35 U.S.C. 103:
“A person of ordinary skill in the art is also a person of ordinary creativity, not an automaton.” KSR, 550 U.S., 82 USPQ2d at 1397. “[I]n many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle.” Office personnel may also take into account “the inferences and creative steps that a person of ordinary skill in the art would employ.”, 82 USPQ2d at 1396.
It would have been obvious to one of ordinary skill in the art, who is also a person of ordinary creativity, to form:
“a second structure arranged on the first structure, and a third structure arranged on the second structure
a second dummy structure arranged on the first dummy structure, and a third dummy structure arranged on the second dummy structure”
because
Kim teaches forming additional GS2 stacks at para. [0079], “In example embodiments, the number of the stack structures and the mold structures stacked in the Z-direction may be varied as described above,…”;
Kim teaches forming an additional stack GS3 in fig. 7; and
Duplication of essential working parts of a device (e.g. duplication of additional GS2 stacks) involves only routine skill in the art. See MPEP 2144.04, Legal Precedent as Source of Supporting Rationale, VI. Reversal, Duplication, or Rearrangement of Parts.
One of ordinary skill in the art forming additional GS2 stacks such as a second GS2
stack and a third GS2 stack would arrive at the claimed invention as shown in fig. 6 annotated below.
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Kim teaches:
11. A semiconductor memory device comprising (see fig. 6 annotated):
a first structure (first GS2) formed in a cell array region (R1) of a substrate (101), a second structure (second GS2) arranged on the first structure, and a third structure (third GS2) arranged on the second structure, the first structure including a plurality of first channel pillars (CH1 at first GS2), the second structure including a plurality of second channel pillars (CH1 at second GS2) corresponding to the plurality of first channel pillars, and the third structure (CH1 at third GS2) including a plurality of third channel pillars corresponding to the plurality of second channel pillars; and
a first dummy structure (first GS2) formed in an alignment area (R2) of the substrate, a second dummy structure (second GS2) arranged on the first dummy structure, and a third dummy structure (third GS2) arranged on the second dummy structure, the first dummy structure including a plurality of alignment keys (KP) disposed between a plurality of first dummy pillars (KC2 at first GS2), the second dummy structure including a plurality of second dummy pillars (KC2 at second GS2) corresponding to the plurality of first dummy pillars, the third dummy structure including a plurality of third dummy pillars (KC2 at third GS2) corresponding to the second dummy pillars. See Kim at para. [0001] – [0146], figs. 1-13.
12. The semiconductor memory device of claim 11, wherein the first dummy structure (first GS2), the second dummy structure (second GS2) arranged on the first dummy structure, and the third dummy structure (third GS2) arranged on the second dummy structure are formed in an overlay area (R2) of a scribe lane of the substrate (e.g. region R2 disposed in scribe lane at para. [0030]),
wherein at least the first dummy structure comprises a plurality of sacrificial pillars (e.g. see fig. 1 teaching additional, adjacent KCs) spaced apart from a second plurality of first dummy pillars (KC2 at first GS2) by gap (e.g. see fig. 1 teaching space between adjacent KCs) in the overlay area.
13. The semiconductor memory device of claim 11,
wherein the plurality of first channel pillars (CH1 at first GS2) and the plurality of first dummy pillars (KC2 at first GS2) have a similar shape and a similar structure,
wherein the plurality of second channel pillars (CH1 at second GS2) and the plurality of second dummy pillars (KC2 at second GS2) have a similar shape and a similar structure, and
wherein the plurality of third channel pillars (CH1 at third GS2) and the plurality of third dummy pillars (KC2 at third GS2) have a similar shape and a similar structure.
14. The semiconductor memory device of claim 11, wherein at least one of the first structure, the second structure, and the third structure comprises a plurality of insulating interlayers (120) alternately stacked with a plurality of conductive patterns (130), para. [0029], [0037].
15. The semiconductor memory device of claim 11, wherein at least one of the first dummy structure, the second dummy structure, and the third dummy structure comprises a plurality of insulating interlayers (120) alternately stacked with a plurality of sacrificial layers (118) alternately stacked, para. [0029], [0037].
Allowable Subject Matter
Claims 1-10 and 16-20 allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
14 October 2026
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