DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 07/29/2024 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 07/19/2024 & 05/22/2025. The information disclosed therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, 10-12 & 16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jacob et al (US10665281).
Regarding claim 1, Jacob discloses a method for operating a memory device (FIG 1; col 3, lines 52-60 and claim 18; discloses 100), comprising: receiving, through a first bit line coupled to a first memory cell (BL1 coupled to 120A), a first bit line signal (BL1 signal); receiving, through a second bit line coupled to a second memory cell (BL2 coupled to 120B), a second bit line signal (BL2 signal); and receiving, through a word line coupled to a common transistor shared by the first memory cell and the second memory cell(WL1 coupled to 115A common transistors for 120A and 102B), a word line signal (WL1 signal).
Regarding claim 2, Jacob discloses wherein the first memory cell includes a first storage element and a first transistor (FIG 1; 120A comprising 105A and 110A), and the second memory cell includes a second storage element and a second transistor (FIG 1; 120B comprising 105B and 110B).
Regarding claim 6, Jacob discloses wherein each of the first storage element and the second storage element is a resistor (105A and 105B are resistors).
Regarding claim 10, Jacob discloses a method for operating a memory device(FIG 1; 100), comprising: receiving, through a first bit line coupled to a first memory cell including a first transistor and a first storage element(BL1 coupled to 120A comprising 105A), a first bit line signal(BL1 signal); receiving, through a second bit line coupled to a second memory cell including a second transistor and a second storage element(BL2 coupled to 120B comprising 105B), a second bit line signal(BL2 signal); and receiving, through a word line coupled to a common transistor shared by the first memory cell and the second memory cell (WL1 coupled to 115A common transistors for 120A and 102B), a word line signal (WL1 signal).
Regarding claim 11, Jacob discloses wherein a first end of the first storage element is connected to the first bit line and a second end of the first storage element is connected to a first source/drain of the first transistor(FIG 1; 105A first end connected to BL1 and second end connected to s/d of 110A), and wherein a first end of the second storage element is connected to the second bit line and a second end of the second storage element is connected to a first source/drain of the second transistor(FIG 1; 105B first end connected to BL2 and second end connected to s/d of 110B).
Regarding claim 12, Jacob discloses wherein the first transistor has a second source/drain connected to a center node (110A having s/d connected to a center node e.g., 115A line), and the second transistor has a second source/drain connected to the center node (110ABhaving s/d connected to the center node e.g., 115A line).
Regarding claim 16, Jacob discloses wherein each of the first storage element and the second storage element is a resistor (105A and 105B are resistors).
Allowable Subject Matter
Claims 18-20 are allowed.
Claims 3-5,7-9, 13-15 & 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Haukness et al (US20190371399) discloses a method for operating a memory device (FIG 4), comprising: receiving, through a first bit line coupled to a first memory cell (412 coupled to 416 receiving first BL signal BL comprising 420), a first bit line signal (BL); receiving, through a second bit line coupled to a second memory cell (BL on second 412 connected to 416 comprising 420), a second bit line signal (BL).
Wang et al (US1238779 FIG 4; discloses PXIB connected to the drain of first and second memory cells, wherein PXIB receiving WL1 signal)
Lekomiller et al (US20010004236 FIG 3; [00243] discloses transistors P1, P2, and P4 connected to a cascode gate lines).
Kim et al (US20090219092 FIG 4; [0041] discloses resistors source of transistors are connected to common source node).
Maruyama et al (US20220166309 FIG 6); Gupta et al (US20170133092 FIG 3B-4A); Hong et al (US20110103120 FIG 3)) & Dokania et al (US11770936 FIG 3B).
Cho et al (US20110205802 FIG 2; a memory device including a memory cell and a transistor between a common source line and the memory cell).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
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/MUNA A TECHANE/ Primary Examiner, Art Unit 2827