DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 07/29/2024 have been accepted by the examiner.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 07/29/2024. The information disclosed therein was considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4-5 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the limitations cite, “wherein a second transistor of the pair of transistors is to provide the voltage source to the bit line and a third transistor of the pair of transistors is to couple the sensor to the bit line”, it is unclear how the third transistor of the pair of transistors is used to couple the sensor to the bit line, when in claim 1 the pair of transistors provide only a selected one of a voltage source OR a sensor to a bit line? Please amend in way where claim 1 has both functionalities of claim 4 or claim 4 only has one of the functionalities of claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 & 4-6 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Wang et al (US20100208520).
Regarding claim 1, Wang discloses a memory system(FIG 2; 60), comprising: a pair of transistors to provide a selected one of i) a voltage source or ii) a sensor to a bit line of a memory array according to a pair of signals (SW1, SW2) (FIG 2; [0058 & 0060] Pair transistors 70 and 72, wherein 70 is used to provide a voltage source (programming voltage) using 82, sensing signal to a bit line 102 that 84 is used for sensing to a memory array 60 e.g., according to a pair of signals 82 and 84 on 74 using 84); and a transistor to couple the pair of transistors to the bit line according to a bias signal (FIG 2; [0064] discloses bias voltage being applied to line of transistor 74).
Regarding claim 2, Wang discloses further comprising: a plurality of memory cells connected to the bit line (FIG 2; 102 connected to the plurality of memory cells in 60).
Regarding claim 4, Wang discloses wherein the transistor is a first transistor (74), and wherein a second transistor of the pair of transistors is to provide the voltage source to the bit line and a third transistor of the pair of transistors is to couple the sensor to the bit line (FIG 2; [0058 & 0060] discloses sensing voltage on 84 provided to 72 and programming voltage on 82 provided to 70).
Regarding claim 5, Wang discloses wherein respective source/drain terminals of the second transistor and the third transistor are coupled to a first source/drain terminal of the first transistor (FIG 2; s/d of 70 and 72 are coupled to s/d of 74). Note the word coupled can mean, anything on the electrical circuit is coupled to one another and a design choice can also be applied here).
Regarding claim 6, Wang discloses further comprising: a bias controller circuit configured to provide the bias signal to a gate terminal of the transistor (FIG 2; [0064] discloses Vbias is applied to the line of 90 that is connected to the gate of 90).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 & 7-12, 14-18 & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al in view of Tran et al (US20190355420).
Regarding claim 3 Wang discloses herein the plurality of memory cells comprise (FIG 2; 60).
However, Wang does not disclose a resistive memory device.
In the same field of endeavor, Tran discloses a resistive memory device (FIG 4; resistive memory element).
Wang and Tran disclose are analogous art because they are all directed to a non-volatile memory device with power source flowing through transistors, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Wang to include Tran because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Tran in the teachings of Wang for the benefits avoiding inaccurate data readings during a memory operation and improving an accuracy with data which data is written to or read from the non-volatile memory device. [0003 Tran]
Regarding claim 7, the combinations of Wang and Tran disclose further comprising: a memory controller coupled to respective gate terminals of (Tran FIG 1 & 4; 163 coupled to respective gate terminal of transistor) the pair of transistors (Wang FIG 2; pair of transistors 70 & 72).
Regarding claim 8, the combinations of Wang and Tran disclose wherein the memory controller (Tran 163) is further configured to generate pulse signals to activate one of the pair of transistors (Wang FIG 2-3; voltage level e.g., pulses on 70 & 74).
Regarding claim 9, the combinations of Wang and Tran disclose further comprising: an amplifier comprising a first input coupled to the bit line and an output coupled to the transistor, wherein the amplifier is configured to generate the bias signal (Tran FIG 4; 402 generating bias signals for 302).
Regarding claim 10, the combinations of Wang and Tran disclose wherein the amplifier comprises a second input coupled to a control input (FIG 402; comprising second input coupled to a control input).
Regarding claim 11, the combinations of Wang and Tran disclose further comprising a temperature-controlled current source (FIG 4; [0038] comprises temperature coefficient TC of IR drop, e.g., current is tuned to correct for variation due to temperature effects).
Regarding claim 12, Wang discloses a method, comprising: , a first switching signal to a gate terminal of a first transistor to couple a voltage source to a bit line coupled to a memory cell; responsive to providing the first switching signal for a first duration, providing, , a second switching signal to a gate terminal of a second transistor to couple a sensor to the bit line; wherein the sensor is configured to sense current through the memory cell during a second duration after the first duration (FIG 2; [0058 & 0060] Pair transistors 70 and 72 to provide a voltage source (programming voltage) on 70 e.g, on programming duration by 82, and sensing on 72 by 84 with 74).
However, Wang does not disclose a memory controller.
In the same field of endeavor, Tran discloses a memory controller (FIG 1; 163).
Wang and Tran disclose are analogous art because they are all directed to a non-volatile memory device with power source flowing through transistors, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Wang to include Tran because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Tran in the teachings of Wang for the benefits avoiding inaccurate data readings during a memory operation and improving an accuracy with data which data is written to or read from the non-volatile memory device. [0003 Tran]
Regarding claim 14, the combinations of Wang and Tran disclose further comprising: providing, by the memory controller (Tran FIG 1;163), a first pulse to a word line of the memory cell Wang (FIG 2-3; voltage level e.g., pulses on 70 & 74).
Regarding claim 15, the combinations of Wang and Tran disclose further comprising: applying a second voltage to the gate terminal of the first transistor during the second duration to electrically decouple the voltage source from the bit line (Wang FIG 2; when sensing the bit line is being done using 84 on 72, the programming using 82 on 70 is decoupled e.g., no programming voltage is applied).
Regarding claim 16, the combinations of Wang and Tran disclose wherein the memory cell is a resistive memory cell (FIG 3; resistive memory element).
Regarding claim 17, the combinations of Wang and Tran disclose wherein the memory cell is a flash memory cell (Tran FIG 2; [0054] discloses 60 flash memory).
Regarding claim 18, Wang discloses a memory system, comprising: a set of memory cells connected to a bit line (FIG 2; 60 comprising memory cells coupled to 102); a switching circuit configured to couple one of a voltage source or a sensor to the bit line (70 & 72 using 82 and 84 with 74); and configured to control the switching circuit to couple the voltage source to the bit line for a first duration (FIG 2;programming using 82 on 70 is coupling 102 e.g., programming voltage is applied).
However, Wang does not disclose a memory controller.
In the same field of endeavor, Tran discloses a memory controller (FIG 1; 163).
Wang and Tran disclose are analogous art because they are all directed to a non-volatile memory device with power source flowing through transistors, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Wang to include Tran because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Tran in the teachings of Wang for the benefits avoiding inaccurate data readings during a memory operation and improving an accuracy with data which data is written to or read from the non-volatile memory device. [0003 Tran]
Regarding claim 20, the combinations of Wang and Tran disclose wherein the memory controller (Tran FIG 1; 163) is further configured to control the switching circuit to couple the sensor to the bit line for a second duration following the first duration (Wang FIG 2; when sensing the bit line is being done using 84 on 72(second duration), the programming using 82 on 70 is decoupled e.g., no programming voltage is applied).
Claim(s) 13 & 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al in view of Tran et al further in view of Chang et al (US20180358057).
Regarding claim 13, the combinations of Wang and Tran disclose wherein the first switching signal is provided in response to (FIG 2-3; voltage level e.g., pulses on 70 & 74).
However, the combination of Wang in view of Tran do not disclose a first edge of the first pulse (FIG 12-13; first edge of pulse t1-t2).
In the same field of endeavor, Chang discloses a first edge of the first pulse.
Wang in view of Tran and Chang are analogous art because they are all directed to a memory device with amplifier and a bias control signal, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Wang in view of Tran to include Chang because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Chang in the teachings of Wang in view of Tran for the benefits avoiding delays in operation speed of the memory device [0002 Chang].
Regarding claim 19, the combinations of Wang and Tran disclose wherein the memory controller is further configured to couple the voltage source to the bit line for the first duration in response to (Tran FIG 1; 163; Wang FIG 2; when sensing the bit line is being done using 84 on 72).
However, the combination of Wang in view of Tran do not disclose a first edge of the first pulse (FIG 12-13; first edge of pulse t1-t2).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chih et al (US20070041244) discloses a memory system comprising(FIG 3;[0018] 300): a memory cell(memory cell 304); a bit line connected to the memory cell(FIG 3; 310 connected to 304); a pair of transistors to electrically couple(306 and 308), to the bit line(306 and 308 coupled to 310), a selected one of i) a voltage source to bias the memory cell (FIG 3; [0018-0022] VB bias 306 and 308 and voltage applied to the memory cell 316 ) or ii a sensor to sense a current through the memory cell(340); and a first transistor coupled between each of the pair of transistors and the bit line(FIG 3; 318 is coupled between 306 and 308 e.g., the terminal of 308 at the intersection between 306 and 308), and including: a first electrode coupled to the pair of transistors(318 coupled to the node of 312 of 306 and 308), and a second electrode coupled to the bit line(318 bottom side (second electrode) coupled to the bit line (e.g., the node below 318)).
Fastow et al(US20120327717) discloses a memory system comprising(FIG 2; 200): a set of memory cells(200A-202D); a bit line connected to the set of memory cells(BL1 208B connected to 200A-202D); a first transistor connected between a voltage source and the bit line(FIG 2; 206B connected between BL1 208B and 214B) ; and a second transistor connected between a sensor and the bit line (FIG 2; 212A connected between 208B and amplifier region).
Teseng et al (US10510383) discloses a memory system comprising (FIG 13; 1300): a set of memory cells(1336 and 1346); a bit line connected to the set of memory cells(BLQ connected to 1336 and 1346); a first transistor connected between a voltage source and the bit line(FIG 13; discloses transistor 1356 connected between VHLB and BLQ) ; and a second transistor connected between a sensor and the bit line (and transistor 1338 connected between BLQ and sensing enable circuit 1332).
Choi et al (US20130083615 FIG 5; claim 2 discloses isolation transistor connected between the bit line and sense amplifier).
Kurihara et al (US6525969 FIG 8b; discloses BL3 and transistor 672 between current sensor 676 and BL3).
Lambrache et al (US20070189101 FIG 3A), Nishiumura et al (US6587367 FIG 8) & Wadhwa et al (US7397696 FIG 8).
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/MUNA A TECHANE/ Primary Examiner, Art Unit 2827
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