Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US Pub # 2017/0288682).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Ma et al. teach a method comprising: performing a first sensing operation associated with a circuitry on a system on chip (SoC) to determine a first data value associated with the circuitry of the SoC (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0046, SENSA/SENSH is first sensing operation); performing a second sensing operation associated with circuitry of a sensor to determine a second data value associated with the circuitry of the sensor (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0046, SENSB/SENSL is second sensing operation); responsive to the first data value and the second data value being the same data values, determining that a clock margin of the SoC is sufficient (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0046, comparator 134A/B, 234A/B compare data vales for clock frequency / margin); and responsive to the first data value and the second data value being different data values, determine that the clock margin of the SoC is insufficient (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0046, comparator 134A/B, 234A/B compare data vales for clock frequency / margin).
Even though Ma et al. teach an integrated circuit, a memory device, a memory system, an electronic device or system (see paragraph 0016) but silent exclusively about circuitry on a system on chip (SoC).
Gupta et al. teach circuitry on a system on chip (SoC) (see see Fig. 1-4, Paragraph 0020). Hoever, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Gupta et al. to the teaching of Ma et al. where processor or circuitry of Ma et al. would be incorporated into system on chip (SoC) as taught by Gupta et al. in order to improve system performance with noise reduction (see Gupta, paragraph 0061).
Further reason to combine the teachings of Gupta et al. and Ma et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards clock adjustment to efficiently operate memory device.
Regarding claim 2, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ma et al. further teach, further comprising storing, in a data structure, a voltage-frequency operating combination associated with at least one operation of the SoC during the first sensing operation, the second sensing operation, or both (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0038).
Regarding claim 3, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ma et al. further teach, further comprising configuring the SoC to operate at a stored voltage-frequency operating combination that provides a clock margin of the SoC that is sufficient (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0040).
Regarding claim 4, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 3 on which this claim depends.
Ma et al. further teach, wherein the stored voltage-frequency operating combination that provides the clock margin of the SoC that is sufficient is selected based on a particular operating condition of the SoC that corresponds to the stored voltage-frequency operating combination (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0045).
Regarding claim 5, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ma et al. further teach, wherein the second sensing operation is associated with the sensor set to an earlier clock arrival in relation to the first sensing operation (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0041).
Regarding claim 6, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 5 on which this claim depends.
Ma et al. further teach, wherein the earlier clock arrival is imparted by a delay line that is coupled to the circuitry of the SoC (see Fig. 1-9 and paragraph 0002-0004, 0015-0035).
Regarding claim 7, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Ma et al. further teach, wherein the second sensing operation is associated with a sensor set to a later data arrival in relation to the first sensing operation (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0038).
Regarding claim 8, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 7 on which this claim depends.
Ma et al. further teach, wherein the later data arrival is imparted by a delay line that is coupled to at least the circuitry of the sensor (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0040).
Regarding independent claim 9, Ma et al. teach an apparatus, comprising: a controller configured to: perform a first sensing operation associated with circuitry on a system on chip (SoC) to determine a first data value associated with the circuitry of the SoC (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0046, SENSA/SENSH is first sensing operation); perform a second sensing operation associated with circuitry of a sensor to determine a second data value associated with the circuitry of the sensor at the second time window (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0046, SENSB/SENSL is second sensing operation); responsive to the first data value and the second data value being the same data value, determine that a clock margin of the SoC is sufficient (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0046, comparator 134A/B, 234A/B compare data vales for clock frequency / margin); responsive to the first data value and the second data value being different data values, determine that the clock margin of the SoC is insufficient; and storing, in a data structure, a voltage-frequency operating combination associated with at least one operation of the SoC (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0046, comparator 134A/B, 234A/B compare data vales for clock frequency / margin).
Even though Ma et al. teach an integrated circuit, a memory device, a memory system, an electronic device or system (see paragraph 0016) but silent exclusively about circuitry on a system on chip (SoC).
Gupta et al. teach circuitry on a system on chip (SoC) (see see Fig. 1-4, Paragraph 0020). Hoever, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Gupta et al. to the teaching of Ma et al. where processor or circuitry of Ma et al. would be incorporated into system on chip (SoC) as taught by Gupta et al. in order to improve system performance with noise reduction (see Gupta, paragraph 0061).
Further reason to combine the teachings of Gupta et al. and Ma et al. is evidenced by virtue of their common field of endeavor, e.g. both are drawn towards clock adjustment to efficiently operate memory device.
Regarding claim 10, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Ma et al. further teach, wherein: the circuitry in the SoC is a first flip-flop; and the circuitry in the sensor is a second flip-flip (see Fig. 1-9 and paragraph 0002-0004, 0015-0035).
Regarding claim 11, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Ma et al. further teach, wherein the circuitry in the sensor comprises an individual flip-flop (see Fig. 1-9 and paragraph 0002-0004, 0015-0032).
Regarding claim 12, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Ma et al. further teach, wherein the sensor comprises the individual flip-flop in the absence of an additional flip-flop (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037).
Regarding claim 13, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 11 on which this claim depends.
Ma et al. further teach, further comprising a delay line, wherein the delay line is coupled to the circuitry in the SoC or individual flip-flop (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0041).
Regarding claim 14, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Ma et al. further teach, wherein the controller is configured to: incrementally decrease a voltage associated with the SoC until the first sensing operation and the second sensing operation have different data value to determine a base operational voltage of the SoC; or incrementally increase a voltage associated with the SoC until the first sensing operation and the second sensing operation have the same data value to determine the base operational voltage of the SoC (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0046).
Regarding claim 15, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 14 on which this claim depends.
Ma et al. further teach, wherein the base operational voltage of the SoC is substantially equal to a last voltage at which the data values of the first sensing operation and the second sensing operation are the same value (see Fig. 1-9 and paragraph 0002-0004, 0015-0035).
Regarding claim 16, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 10 on which this claim depends.
Ma et al. further teach, wherein the controller is configured to incrementally increase a frequency associated with the SoC until the first sensing operation and the second sensing operation have different data values to determine a threshold operational frequency of the SoC (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0042).
Regarding claim 17, Ma et al. and Gupta et al.teach all claimed subject matter as applied in prior rejection of claim 16 on which this claim depends.
Ma et al. further teach, wherein the threshold operational frequency of the SoC is substantially equal to a last voltage at which the data values of the first sensing operation and the second sensing operation and the same value (see Fig. 1-9 and paragraph 0002-0004, 0015-0035, 0037-0045).
Allowable Subject Matter
Claims 18-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 18 include allowable subject matter since the prior art made of record and considered pertinent to the applicant’s disclosure, taken individually or in combination, does not teach or suggest the claimed invention having:
perform an additional sensing operations to determine: a subsequent data value associated with the flip-flop on the SoC; and a subsequent data value associated with the individual flip-flop of the sensor; store at least one voltage-frequency operating combinations of the SoC associated with the first data value, the second data value, and the subsequent data values, in a data structure; and configure the SoC to operate at one of the stored voltage-frequency operating combinations which provides a sufficient margin.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See attachment.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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