DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi et al. US 2013/0299957 A1.
Regarding claims 1-6, Kobayashi discloses:
A semiconductor device assembly (Figs. 1 and 2) comprising:
a semiconductor device (6a) including an active side (top), a back side (bottom) opposite the active side, and sidewalls extending between the back side and the active side;
a redistribution layer (2a including 22) disposed over and in direct contact with the active side of the semiconductor layer and extending past at least one of the sidewalls of the semiconductor device such that the redistribution layer includes a first portion (portion of a 2a to the right of 6a sidewall) vertically aligned with and electrically coupled to the active side of the semiconductor device (thru 20) and a second portion (portion of 2a to the left of 6a sidewall) not vertically aligned with the active side of the semiconductor device; and
a wirebond contact (21a) formed on the second portion of the redistribution layer.
(claim 2) Figs. 1 and 2; electrically coupled thru 22 and 20.
(claim 3) Figs. 1 and 2; a die pad (20).
(claim 4) para 0068; multiple number of terminals provided.
(claim 5) Figs. 1 and 2; a fan-out porch (1a).
(claim 6) para 0053; extension 1a made of resin.
Regarding claims 7-11, Kobayashi discloses:
A semiconductor device assembly (Figs. 1 and 2) comprising:
a semiconductor device (6a) including an active side (top) and a back side (bottom) opposite the active side;
a fan-out porch (1a) formed separately from the semiconductor device and positioned in direct contact with a lateral side of the semiconductor device; and
a redistribution layer (2a including 22) extending over both the active side of the semiconductor device and the fan-out porch, the redistribution layer including a wirebond contact (21a) disposed over the fan-out porch, the wirebond contact being electrically coupled to the semiconductor device (thru 22 and 20).
(claim 8) Figs. 1 and 2; a die pad (20).
(claim 9) para 0053; extension 1a made of resin.
(claim 10) Fig. 1.
(claim 11) para 0068; multiple number of terminals provided.
Regarding claims 12-15, Kobayashi discloses:
A method of assembling a semiconductor device assembly (Figs. 1 and 2; paras 0053-0056), the method comprising:
forming a fan-out porch (1a) in direct contact with a lateral edge of a semiconductor device (6a);
forming a redistribution layer (2a including 22) extending over both an active side of the semiconductor device and the fan-out porch; and
forming a wirebond contact (21a) on the redistribution layer and vertically aligned with the fan-out porch, the wirebond contact being electrically coupled to the semiconductor device (thru 22 and 20).
(claim 13) para 0053; extension 1a made of resin.
(claim 14) Fig. 1.
(claim 15) para 0068; multiple number of terminals provided.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
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/ERROL V FERNANDES/Primary Examiner, AU 2893
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