DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 9-15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li (US 8455267 B2).
Regarding claim 1, Li teaches a semiconductor structure (800, Fig 8), comprising:
a substrate (102);
a dielectric layer (602) over (shown over) the substrate (102);
a plurality of memory cells (402) disposed in (shown in) the dielectric layer (602),
each of the memory cells (402) including, from bottom to top (shown from bottom to top), a bottom electrode (302), a memory material layer stack (MTJ: 404/406/408; shown as Fix/Barrier/Free in Fig 8), and a top electrode (TE: 502/704); and
a metal line (ML: 702/706) above (shown above) the memory cells (402),
a bottom surface (MLB: bottom surface of ML) of the metal line (ML) having a continuously flat portion (702B: bottom surface of 702) that directly interfaces (shown in direct contact) each of the top electrodes (TE) of the memory cells (402).
Regarding claim 2, Li teaches the structure of claim 1 and goes on to teach wherein the memory material layer stack (MTJ, Fig 8) provides a magnetic tunnel junction (MTJ, [Col 5, Ln 25-28]).
Regarding claim 3, Li teaches the structure of claim 1 and goes on to teach wherein the memory cells (402, Fig 8) are arranged in a row (shown arranged in a row).
Regarding claim 4, Li teaches the structure of claim 1 and goes on to teach wherein the bottom surface (MLB, Fig 8) of the metal line (ML) has a second portion (706B: bottom surface of 706) that is lower (shown lower) than the continuously flat portion (702B).
Regarding claim 6, Li teaches the structure of claim 4 and goes on to teach wherein the second portion (706B, Fig 8) of the bottom surface (MLB) of the metal line (ML) is below (shown below) bottom surfaces (502B: bottom surface of 502) of the top electrodes (TE) of the memory cells (402).
Regarding claim 7, Li teaches the structure of claim 1 and goes on to teach wherein the substrate (102, Fig 8) includes a memory region (108) and a logic region (110),
the memory cells (402) are positioned in (shown in) the memory region (108), and
the metal line (ML) extends into (shown extended into) the logic region (110).
Regarding claim 9, Li teaches the structure of claim 7 and goes on to teach wherein the metal line (ML, Fig 8) has a first thickness (T1: maximum vertical thickness of 702) in (shown in) the memory region (108) and
a second thickness (T2: Maximum thickness from top of 702 (shown as Top Cu Metal) to bottom of 706) in (shown in) the logic region (110), and
the first thickness (T1) is smaller (shown smaller) than the second thickness (T2).
Regarding claim 10, Li teaches the structure of claim 1 and goes on to teach further comprising:
a via (V1: via for portion of 702 shown in logic region 110, labeled as Top Cu Metal) landing on (shown landing on) a top surface (706T: top surface of 706) of the metal line (ML), wherein
the via (V1) is laterally offset (shown laterally offset) from an edge (702R: right sidewall of 702) of the continuously flat portion (702B) of the bottom surface (MLB) of the metal line (ML).
Regarding claim 11, Li teaches a semiconductor device (800, Fig 8), comprising:
an array of memory cells (402) over (shown over) a substrate (102),
each of the memory cells (402) including a bottom electrode (302), a magnetic tunnel junction (MTJ: 404/406/408; shown as Fix/Barrier/Free in Fig 8), and a top electrode (TE: 502/704);
an encapsulation layer (602) covering (shown covering) sidewalls (402SW: vertical sidewalls of 402) of the memory cells (402);
a memory-level dielectric layer (604) over (shown over) the encapsulation layer (602); and
a metal line (ML: 702/706) embedded in (shown embedded in) the memory-level dielectric layer (604),
the metal line (ML) having a portion of a bottom surface (702B: bottom of 702) that is continuously flat (shown continuously flat) and physically contacting (shown in contact) the top electrodes (TE) of a row (shown in a row) of the memory cells (402).
Regarding claim 12, Li teaches the device of claim 11 and goes on to teach wherein the portion of the bottom surface (702B, Fig 8) of the metal line (ML) also physically contacts (shown in contact) a top surface (602T: top surface of 602) of the encapsulation layer (602).
Regarding claim 13, Li teaches the device of claim 11 and goes on to teach wherein the metal line (ML, Fig 8) has a first segment (702) directly above (shown directly above) the row of the memory cells (402) and
a second segment (SS: 702R/706 where 702R is the portion of 702 directly connected to 706 in 110) laterally offset (shown laterally offset) from the row of the memory cells (402), and wherein
the first segment (702) and the second segment (SS) of the metal line (ML) have different thicknesses (shown with different thicknesses).
Regarding claim 14, Li teaches the device of claim 13 and goes on to teach wherein the second segment (SS, Fig 8) is thicker (shown thicker) than the first segment (702).
Regarding claim 15, Li teaches the device of claim 13 and goes on to teach further comprising:
an etch stop layer (106, Fig 8) disposed on (shown on) the metal line (ML); and
a via (V2: via for 202) extending through (shown extending through) the etch stop layer (106) and landing on (shown landing on) the second segment (SS) of the metal line (ML).
Regarding claim 17, Li teaches A semiconductor structure (800, Fig 8) comprising:
a memory region (108) comprising:
a dielectric layer (604);
a row (shown in a row) of memory cells (402) disposed in (shown in) the dielectric layer (604),
each of the memory cells (402) including a top electrode (TE: 502/704);
a common top electrode (ML: 702/706) having a bottom surface (702B: bottom of 702) that has a continuously flat portion (702BP: continuously flat portion of 702B),
the continuously flat portion (702BP) directly interfacing (shown directly interfacing) the dielectric layer (604) and the top electrodes (TE) of the row of memory cells (402); and
an etch stop layer (602) disposed directly on (shown directly on) the dielectric layer (604) and the common top electrode (ML).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 8455267 B2) as applied to claim 17 above, and further in view of Yin (US 20210391532 A1).
Regarding claim 18, Li teaches the structure of claim 17, the dielectric layer (604), and goes on to teach a logic region (110, Fig 8).
Li fails to explicitly teach a transistor directly under the dielectric layer.
However, Yin teaches a transistor (Tr1: transistor shown farthest right, Fig 21) directly under (directly under; the dielectric layer 604 of Li extends to the logic region) the dielectric layer.
Li then goes on to teach wherein the common top electrode (ML) extends into (shown extended into) the logic region (110) and electrically coupled to the transistor.
Li and Yin are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor structures. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Li with the features of Yin to create a logic region with a transistor directly under the dielectric layer because electrical shorts between the materials of the patterned layer stacks are mitigated in order to provide functional memory devices (Yin, [0002]) in order to minimize the size and power consumption while maximizing speed and performance (Yin, [0032]).
Regarding claim 19, the combination of Li and Yin discloses the structure of claim 18. Li goes on to teach wherein the common top electrode (ML, Fig 8) has a larger thickness (shown with a larger thickness) in (shown in) the logic region (10) than in the memory region (108).
Regarding claim 20, the combination of Li and Yin discloses the structure of claim 18. Li goes on to teach wherein the logic region (110, Fig 8) further comprises a via (V2: via for 202) through the etch stop layer (602) and landing on (shown landing on) the common top electrode (ML).
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 8455267 B2) as applied to claims 1 and 11 above, and further in view of Dutta (US 20210134883 A1).
Regarding claim 5, Li teaches the structure of claim 4, the bottom surface (MLB, Fig 8) of the metal line (ML), the continuously flat portion (702B), and the second portion (706B).
Li fails to explicitly teach the bottom surface of the metal line has a slanted portion adjoining the continuously flat portion and the second portion.
However, Dutta teaches wherein the bottom surface of the metal line has a slanted portion (506B: bottom surface of 506, shown slanted, Fig 8) adjoining (shown adjoining; the top portion of 506 is analogous to the continuously flat portion of Li shown in memory region 124 labeled in Fig 1, while 406/404 are analogous to the second portion of Li shown in logic region 122/125 labeled in Fig 1) the continuously flat portion and the second portion.
Li and Dutta are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor structures. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Li with the features of Dutta to create a structure wherein the bottom surface of the metal line has a slanted portion adjoining the continuously flat portion and the second portion with advantages such as reduced chip number, increased response times, etc. (Dutta, [0002]) and allow for longer IBE over-etch and clean-up to be performed resulting in no electrode footing or metal residue on the MTJ sidewall (Dutta, [0026]).
Regarding claim 16, Li teaches the device of claim 11, the memory-level dielectric layer (604), and goes on to teach wherein a bottom surface (602B: bottom of 602, Fig 8) of the encapsulation layer (602) is below (shown below) bottom surfaces (302B: bottom of 302) of the bottom electrodes (302) of the memory cells (402).
Li fails to explicitly teach a bottom surface of the memory-level dielectric layer is below the bottom surface of the encapsulation layer.
However, Dutta teaches a bottom surface (126B: bottom of 126, Fig 8) of the memory-level dielectric layer is below (shown below: memory-level dielectric 126 is shown with a bottom surface below encapsulation 310) the bottom surface of the encapsulation layer.
Li and Dutta are considered analogous to the claimed invention because both are from the same field of endeavor of semiconductor structures. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Li with the features of Dutta to create a structure wherein a bottom surface of the memory-level dielectric layer is below the bottom surface of the encapsulation layer with advantages such as reduced chip number, increased response times, etc. (Dutta, [0002]) and allow for longer IBE over-etch and clean-up to be performed resulting in no electrode footing or metal residue on the MTJ sidewall (Dutta, [0026]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Li (US 8455267 B2) as applied to claim 7 above, in view of Yin (US 20210391532 A1), and further in view of Dutta (US 20210134883 A1).
Regarding claim 8, Li teaches the structure of claim 7, the memory region (108, Fig 8), the logic region (110), the top electrode (TE), and the metal line (ML)..
Li fails to explicitly teach the memory region includes a first transistor, the logic region includes a second transistor, and the second transistor is electrically coupled to the top electrode of the first one of the memory cells through the metal line.
However, Yin teaches wherein the memory region includes a first transistor (750, Fig 21),
the logic region includes a second transistor (Tr2: non-labeled transistor to the right of 750 in the logic region).
Li then goes on to teach the first transistor is electrically coupled (electrically coupled when combined with Lin) to the bottom electrode (302) of a first one (402A: 402 on right closest to 110) of the memory cells (402).
Dutta teaches the second transistor is electrically coupled (shown electrically coupled, Fig 8; metal line 506 extends from the memory region 124, shown in Fig 1, to the logic region 122/125 and connects to top electrode 302 of the memory cell) to the top electrode of the first one of the memory cells through (shown connected through, the metal line 506 would connect to the second transistor through 114) the metal line.
Li, Yin, and Dutta are considered analogous to the claimed invention because all are from the same field of endeavor of semiconductor structures. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Li with the features of Yin and Dutta to create a structure wherein the memory region includes a first transistor, the logic region includes a second transistor, and the second transistor is electrically coupled to the top electrode of the first one of the memory cells through the metal line because electrical shorts between the materials of the patterned layer stacks are mitigated in order to provide functional memory devices (Yin, [0002]) in order to minimize the size and power consumption while maximizing speed and performance (Yin, [0032]) with advantages such as reduced chip number, increased response times, etc. (Dutta, [0002]) and allow for longer IBE over-etch and clean-up to be performed resulting in no electrode footing or metal residue on the MTJ sidewall (Dutta, [0026]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shen (US 20220059759 A1) - MTJ top electrode
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights