DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 08/04/2026 and 01/14/2026, is/are in compliance with the provisions 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Components 104 and 105 are shown in Figs. 1 and 12, but are not mentioned in the Specification. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1- 4, 8-11, 13-14, 16, 19, 21, 22, 24-26 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin et al. (US 20210057607) herein referred to as Lin
As to claim 1, Lin teaches a micro light emitting diode (LED) structure, comprising:
a mesa structure (Fig. 2H-2K), comprising:
a first type semiconductor layer having a first conductive type ([0232]Fig. 2J, 203: first type semiconductor layer);
a light emitting layer ([0234] Fig. 2J, 103: light emitting layer) formed on the first semiconductor layer (203); and
a second type semiconductor layer ([0233] Fig. 2J, 101: second type semiconductor layer) formed on the light emitting layer (103),
the second type semiconductor layer (101) having a second conductive type different from the first conductive type (The materials listed in [0880] can accommodate both n-type and p-type doping [0880]
“The first type semiconductor layer 101, the second type semiconductor layer 102 and the light emitting layer 103 of the above-mentioned micro light emitting diodes may include any materials, for example including gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), aluminumgallium indium nitride (AlGaInN), gallium phosphide (GaP), aluminum phosphide (AlP), aluminum gallium phosphide (AlGaP), aluminum arsenide (AlAs), aluminum gallium arsenide (AlGaAs), aluminumindium gallium phosphide (AlInGaP), aluminumindium gallium arsenide (AlInGaAs), zinc selenide (ZnSe), zinc oxide (ZnO) or the alloy thereof, but not limit thereto.); wherein
a top surface area of the second type semiconductor layer (Fig. 2I, top of layer 101) is greater than each of:
a bottom surface area of the first semiconductor layer (Fig. 2I, bottom of layer 102),
a top surface area of the first semiconductor layer (Fig. 2I, top of layer 102), and
a bottom surface area of the second semiconductor layer (Fig. 2J, bottom of layer 101); and wherein,
the first type semiconductor layer (102) comprises:
a semiconductor region ([0230] lists current limiting implantation areas [0241] 203: third current limiting area, can be of the first type depending of doping choice of [0880]); and
an ion implantation region formed around the semiconductor region (area surrounding (203) in the 1st type layer).
PNG
media_image1.png
405
1063
media_image1.png
Greyscale
As to claim 2, Lin teaches the micro LED structure according to claim 1, as discussed above, and further comprising:
a top contact (304) ([0623] Fig. 2I, 304: “The back electrode 304 may include a multi-layer structure, which includes an ohm contact layer”) formed on the top surface of the second semiconductor layer (101), the top contact (304) having the second conductive type; and
a bottom contact (302/303) (Fig. 2I, [0623] The Micro-LED device may further include an electrode 302 located above the second type semiconductor layer 102… In such condition, an electrode extension part 303 located above the transparent electrode 301 can be further included, wherein the electrode extension part 303 is electrically connected to the electrode 302”)
formed on the bottom surface of the first semiconductor layer(102), the bottom contact (302/303) having the first conductive type wherein
the semiconductor region (203) is formed on a top surface of the bottom contact (302)
As to claim 3, Lin teaches the micro LED structure according to claim 2, as discussed above, and further discloses wherein
a center of the bottom contact (302/303), a center of the top contact (304), and a center of the semiconductor region (203) are aligned (Fig. 2I) along a same axis perpendicular to the top surface of the second semiconductor layer (101), and wherein
a diameter (Fig. 2I) of the ion implantation region (102) is greater than or equal to a diameter of the bottom contact (302/303).
As to claim 4, Lin teaches the micro LED structure according to claim 2, as discussed above, and further discloses:
a top conductive layer (top conductive layers is one of the conductive layers of 304 [0623] ”The back electrode 304 may include a multi-layer structure, which includes an ohm contact layer, a diffusion blocking layer, a connecting layer and a reflective mirror layer.”) formed on the second type semiconductor layer (101) and the top contact (304).
As to claim 8, Lin teaches the micro LED structure according to claim 1, as discussed above, and further discloses wherein
the mesa structure comprises a flat sidewall (Fig. 2I).
As to claim 9, Lin teaches the micro LED structure according to claim 1, as discussed above, and further discloses wherein
the ion implantation region (102) comprises at least one type of implanted ions ([0879] “For example, the materials used in the above-mentioned ion implantation technique may include ions H.sup.+, He.sup.+, N.sup.+, F.sup.+, Mg.sup.+, Ar.sup.+, Zn.sup.+, O.sup.+, Si.sup.+, P.sup.+, Be.sup.+, C.sup.+, B.sup.+, P.sup.+, As.sup.+, Sb.sup.+, Te.sup.+, Fe.sup.+, Co.sup.+, Sn.sup.+, Zr.sup.+, Ag.sup.+, Au.sup.+, Ti.sup.+, Al.sup.+ or the combination thereof, but not limited thereto.).
As to claim 10, Lin teaches the micro LED structure according to claim 9, as discussed above, and further discloses wherein
the implanted ions are selected from one or more of the following ions: hydrogen, nitrogen, fluorine, oxygen, carbon, argon, phosphorus, boron, silicon, sulfur, arsenic, chlorine, and metal ions ([0879] For example, the materials used in the above-mentioned ion implantation technique may include ions H.sup.+, He.sup.+, N.sup.+, F.sup.+, Mg.sup.+, Ar.sup.+, Zn.sup.+, O.sup.+, Si.sup.+, P.sup.+, Be.sup.+, C.sup.+, B.sup.+, P.sup.+, As.sup.+, Sb.sup.+, Te.sup.+, Fe.sup.+, Co.sup.+, Sn.sup.+, Zr.sup.+, Ag.sup.+, Au.sup.+, Ti.sup.+, Al.sup.+ or the combination thereof, but not limited thereto.)
As to claim 11, Lin teaches the micro LED structure according to claim 10, as discussed above, and further discloses wherein
the metal ions are selected from one or more of zinc, copper, indium, aluminum, nickel, titanium, magnesium, chromium, gallium, tin, antimony, tellurium, tungsten, tantalum, germanium, molybdenum, and platinum ([0879] For example, the materials used in the above-mentioned ion implantation technique may include ions H.sup.+, He.sup.+, N.sup.+, F.sup.+, Mg.sup.+, Ar.sup.+, Zn.sup.+, O.sup.+, Si.sup.+, P.sup.+, Be.sup.+, C.sup.+, B.sup.+, P.sup.+, As.sup.+, Sb.sup.+, Te.sup.+, Fe.sup.+, Co.sup.+, Sn.sup.+, Zr.sup.+, Ag.sup.+, Au.sup.+, Ti.sup.+, Al.sup.+ or the combination thereof, but not limited thereto.)
As to claim 13, Lin teaches the micro LED structure according to claim 1, as discussed above, and further discloses wherein
a thickness of the light emitting layer (Fig. 2I, 103) is less than a thickness of the first semiconductor layer (Fig.2I, 102).
As to claim 14, Lin teaches the micro LED structure according to claim 1, as discussed above, and further discloses wherein
the light emitting layer (Fig.2J, 103) is formed by a quantum well layer ([0772] The light emitting layer includes single-layer quantum well structure or multi-layer quantum well structure.) located between the first type semiconductor layer and the second semiconductor layer
As to claim 16, Lin teaches the micro LED structure according to claim 14, as discussed above, and further discloses wherein
the quantum well layer comprises three or less than three pairs of quantum wells (Fig. 9-14 shows 1 quantum well per phosphor color. See [0270] F1: first phosphor with adhesive [0271] F2: second phosphor with adhesive [0272] F3: third phosphor with adhesive [0924] “The light emitting layer includes single-layer quantum well structure or multi-layer quantum well structure.” See also OA appendix which also teaches “Monolithic multicolor, multi-quantum well structure LED” wherein one quantum well has one color.)
As to claim 19, Lin teaches the micro LED structure according to claim 1, as discussed above, and further discloses wherein
the first conductive type is P type and the second conductive type is N type (Implicitly, the materials listed in [0880] can accommodate both n-type and p-type doping [0880].
As to claim 21, Lin teaches a micro display panel, as discussed above, and further discloses comprising:
a micro light emitting diode (LED) array, comprising: a first micro LED structure according to claim 1, the first micro LED structure comprising a first mesa structure (Fig. 2H-2K); and
an integrated circuit (IC) back plane formed under the first micro LED structure, wherein the first micro LED structure is electrically coupled to IC back plane ([0799] Fig. 9-14 “the micro light emitting diodes on the permanent substrate 820”).
As to claim 22, Lin teaches the micro display panel according to claim 21, as discussed above, and further discloses wherein
the micro LED structure further comprising: a connected hole (Fig. 28-17 hole surrounding (304)), wherein a first side of the connected hole is connected to the bottom contact (304), and
a second side of the connected hole is connected to the IC back plane (820).
As to claim 24, Lin teaches the micro display panel according to claim 23, as discussed above, and further discloses wherein
material of the dielectric layer is at least one of SiO2, Si3N4, Al2O3, AlN, HfO2, TiO2 and ZrO2. (Fig. 2Q, [1048] “The current blocking area is composed of dielectric material such as silicon nitride, silicon dioxide or aluminum oxide (Al.sub.2O.sub.3), and the sidewall-covering region of the current blocking area of the present invention has an arc,” [0315] 501: first current blocking area [0316] 502: second current blocking area [0317] 503: third current blocking area [0318] 504: fourth current blocking area [0319] 505: fifth current blocking area [0320] 506: sixth current blocking area [0321])
As to claim 25, Lin teaches the micro display panel according to claim 23, as discussed above, and further comprising
a reflective structure ([0623] “The back electrode 304 may include a multi-layer structure, which includes an ohm contact layer, a diffusion blocking layer, a connecting layer and a reflective mirror layer.”) formed in the dielectric layer and between the first and second mesa structures, wherein the reflective structure does not contact the first and second mesa structures. (See Fig. 9-11)
As to claim 26, Lin teaches the micro display panel according to claim 25, as discussed above, and further discloses wherein
the reflective structure ([0623] “The back electrode 304 may include a multi-layer structure, which includes an ohm contact layer, a diffusion blocking layer, a connecting layer and a reflective mirror layer.”) has: a top surface aligned with top surfaces of the first and second mesa structures (See Fig. 9-11); and
a bottom surface aligned with bottom surfaces of the first and second mesa structures (See Fig. 9-11)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. All obviousness rationales stated below are rationales that would have been obvious prior to the earliest effective filing date of the application.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 6, 7, 12, 15, 20, 23, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20210057607)
As to claim 6, Lin teaches the micro LED structure according to claim 5, as discussed above, and further discloses wherein
the diameter (obvious) of the semiconductor region (Fig. 2I, 203) is less than or equal to three times of the diameter of the bottom contact (Fig. 2I, 302/303); and
the diameter (obvious) of the ion implantation region (Fig. 2I, 102) is greater than two times of the diameter of the semiconductor region (Fig. 2I, 203).
Optimizing the diameter of the semiconductor region is essential because the diameter directly governs the electrical, optical, and thermal behavior of the device.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the diameter of the semiconductor region to be less than or equal to three times of the diameter of the bottom contact and to optimize the diameter of the ion implantation regions to be greater than two times of the diameter of the semiconductor region, so as to improve device performance, reduce leakage current, and prevents short-channel effects.
Furthermore, the Applicant has not shown that the diameter of the semiconductor region and diameter of the ion implantation regions are novel and would not have been found through routine experimentation. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
As to claim 7, Lin teaches the micro LED structure according to claim 5 as discussed above.
Lin does not appear to expressly disclose:
the thickness (obvious) of the semiconductor region ranges from 600nm to 900nm, the thickness of the ion implantation region ranges from 500nm to 800nm,
the diameter (obvious) of the ion implantation region ranges from 500nm to 1250nm, and the diameter of the bottom contact ranges from 20nm to 500nm.
Optimizing the thickness of the semiconductor region is essential because it directly controls how the material absorbs light, conducts electricity, and handles heat.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the thickness of the semiconductor region ranges from 600nm to 900nm, the thickness of the ion implantation region ranges from 500nm to 800nm, the diameter of the ion implantation region ranges from 500nm to 1250nm, and the diameter of the bottom contact ranges from 20nm to 500nm, so as to directly control how the material absorbs light, conducts electricity, and handles heat.
Furthermore, the Applicant has not shown that the thicknesses and diameters are novel and would not have been found through routine experimentation. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
As to claim 12, Lin teaches the micro LED structure according to claim 1 as discussed above.
Lin does not appear to expressly disclose:
a thickness (obvious) of the first type semiconductor layer ranges from 700nm to 2μm and a thickness (obvious) of the second type semiconductor layer ranges from 100nm to 200nm.
Optimizing the thickness of the semiconductor region is essential because it directly controls how the material absorbs light, conducts electricity, and handles heat.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the thickness of the first type semiconductor layer ranges from 700nm to 2μm and a thickness of the second type semiconductor layer ranges from 100nm to 200nm , so as to directly control how the material absorbs light, conducts electricity, and handles heat.
Furthermore, the Applicant has not shown that a thickness of the first type semiconductor are novel and would not have been found through routine experimentation. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233. )
As to claim 15, Lin teaches the micro LED structure according to claim 14 as discussed above.
Lin does not appear to expressly disclose:
a thickness (obvious) of the quantum well layer is less than or equal to 30nm.
Optimizing the thickness of the semiconductor region is essential because it directly controls how the material absorbs light, conducts electricity, and handles heat.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize a thickness of the quantum well layer to be less than or equal to 30nm so as to directly control how the material absorbs light, conducts electricity, and handles heat.
Furthermore, the Applicant has not shown that a thickness of the quantum well layer being less than or equal to 30nm is novel and would not have been found through routine experimentation. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.)
As to claim 20, Lin teaches the micro LED structure according to claim 1 as discussed above.
Lin does not appear to expressly disclose: “the ion implantation region having a resistance higher than (obvious) a resistance of the semiconductor region”.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the ion implantation region resistance to higher than the underlying semiconductor region when your goal is electrical isolation or current confinement, such as in the method of ion implementation of the Lin device in order to optimize the device reliability/design and connectivity requirements.
As to claim 23, Lin teaches the micro display panel according to claim 21, as discussed above and further discloses
the dielectric layer is not conductive [0731] listed dielectric materials are not conductive) and is formed between the first and second mesa structures (such as Fig. 9-14.)
Lin does not appear to expressly disclose “a dielectric layer, wherein the second mesa structure is located adjacent (obvious) to the first mesa structure,” Lin discloses a micro LED structure according to claim 1. However, drawings do not show the plurality of mesa structures in the Lin device. Figure 2I is not shown as a plurality of well structures such as is shown for the non-mesa structures, such as the Fig. 9-1 through 9-14.
Nonetheless, It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to have a plurality of mesa structures wherein the second mesa structure is located adjacent to the first mesa structure as the plurality of non-mesa designs is shown in Figures 9-11-9-14 of the Lin device. [0007] “ The diode array comprises a substrate and a plurality of light emitting diodes disposed on the substrate and arranged in an array, wherein each of the light emitting diodes includes a stack of functional layers comprising a first type semiconductor layer, a second type semiconductor layer, and a light emitting layer located between the first type semiconductor layer and the second type semiconductor layer”
As to claim 27, Lin teaches the micro display panel according to claim 23 as discussed above.
Lin does not appear to expressly disclose: “top surfaces of the first and second mesa structures are separated by a distance less than or equal to 200 nm”
Optimizing the distance between the top surfaces of the first and second mesa structures is crucial for balancing electrical efficiency, optical performance, and strain management.
It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to optimize the distance between the top surfaces of the first and second mesa structures so as to balance electrical efficiency and yield optical performance.
In micro-LEDs, current crowding frequently occurs near the edges of electrodes and contacts. Optimizing the exact difference between the first mesa and the second mesa top surface is crucial for uniform current spreading, lowering device resistance and preventing localized overheating.
Furthermore, the Applicant has not shown that a top surfaces of the first and second mesa structures distance of less than or equal to 200 nm is novel and would not have been found through routine experimentation. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re AIler, 105 USPQ 233.)
Allowable Subject Matter
Claim(s) 5, 17 and 18 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 5, Lin teaches the micro LED structure according to claim 2 as discussed above, wherein
a diameter of the ion implantation region (Fig. 2J, 102) is greater than a diameter of the semiconductor region (203).
Lin does not teach,:
“a thickness of the semiconductor region is greater than or equal to a thickness of the ion implantation region.”
“a diameter of the semiconductor region is greater than or equal to a diameter of the bottom contact”, and
As to claim 17, Lin teaches the micro LED structure according to claim 1 as discussed above.
Lin does not teach “a first reflective mirror formed on the bottom surface of the first semiconductor layer”
As to claim 18, Lin does not teach the micro LED structure according to claim 17 comprising
a second reflective mirror formed inside of the first semiconductor layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
Prosecution Insights